Samsung S3P80C5, User Manual

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S3P80C5/C80C5/C80C8 CONTROL REGISTERS
4-27
T0CON
— Timer 0 Control Register D2H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET RESET
Value
0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.6 Timer 0 Input Clock Selection Bits
0 0 f
OSC
/4096
0 1
f
OSC
/256
1 0
f
OSC
/8
1 1 External clock input (at the T0CK pin, P2.1)
.5–.4 Timer 0 Operating Mode Selection Bits
0 0 Interval timer mode (counter cleared by match signal)
0 1 Overflow mode (OVF interrupt can occur)
1 0 Overflow mode (OVF interrupt can occur)
1 1 PWM mode (OVF interrupt can occur)
.3 Timer 0 Counter Clear Bit
0 No effect (when write)
1 Clear T0 counter, T0CNT (when write)
.2
Timer 0 Overflow Interrupt Enable Bit
(note)
0 Disable T0 overflow interrupt
1 Enable T0 overflow interrupt
.1 Timer 0 Match Interrupt Enable Bit
0 Disable T0 match interrupt
1 Enable T0 match interrupt
.0 Timer 0 Match Interrupt Pending Flag
0 No T0 match interrupt pending (when read)
0 Clear T0 match interrupt pending condition (when write)
1 T0 match interrupt is pending (when read)
1 No effect (when write)
NOTE : A timer 0 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 0
match/ capture interrupt, IRQ0, vector FCH, must be cleared by the interrupt service routine.