Samsung S3P80C5, User Manual

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CONTROL REGISTERS S3P80C5/C80C5/C80C8
4-2
Table 4-1. Mapped Registers (Set 1)
Register Name Mnemonic Decimal Hex R/W
Timer 0 counter T0CNT 208 D0H
R
(note)
Timer 0 data register T0DATA 209 D1H R/W
Timer 0 control register T0CON 210 D2H R/W
Basic timer control register BTCON 211 D3H R/W
Clock control register CLKCON 212 D4H R/W
System flags register FLAGS 213 D5H R/W
Register pointer 0 RP0 214 D6H R/W
Register pointer 1 RP1 215 D7H R/W
Locations D8H is not mapped.
Stack pointer (low byte) SPL 217 D9H R/W
Instruction pointer (high byte) IPH 218 DAH R/W
Instruction pointer (low byte) IPL 219 DBH R/W
Interrupt request register IRQ 220 DCH
R
(note)
Interrupt mask register IMR 221 DDH R/W
System mode register SYM 222 DEH R/W
Register page pointer PP 223 DFH R/W
Port 0 data register P0 224 E0H R/W
Port 1 data register P1 225 E1H R/W
Port 2 data register P2 226 E2H R/W
Location E3H–E6H is not mapped.
Port 0 pull-up resistor enable register P0PUR 231 E7H R/W
Port 0 control register (high byte) P0CONH 232 E8H R/W
Port 0 control register (low byte) P0CONL 233 E9H R/W
Port 1 control register (high byte) P1CONH 234 EAH R/W
Port 1 control register (low byte) P1CONL 235 EBH R/W
Port 1 pull-up resistor enable register P1PUR 236 ECH R/W
Location EDH–EFH is not mapped.
Port 2 control register P2CON 239 F0H R/W
Port 0 interrupt enable register P0INT 241 F1H R/W
Port 0 interrupt pending register P0PND 242 F2H R/W
Counter A control register CACON 243 F3H R/W
Counter A data register (high byte) CADATAH 244 F4H R/W
Counter A data register (low byte) CADATAL 245 F5H R/W
Timer 1 counter register (high byte) T1CNTH 246 F6H
R
(note)
Timer 1 counter register (low byte) T1CNTL 247 F7H
R
(note)
Timer 1 data register (high byte) T1DATAH 248 F8H R/W