Samsung S3F80P5X, User Manual

Page: 261 / 321

S3F80P5_UM_ REV1.00 COUNTER A
COUNTER A CONTROL REGISTER (CACON)
The counter A control register, CACON, is located in F3H, Set 1, Bank 0, and is read/write addressable. CACON
contains control settings for the following functions (See Figure 12-2):
— Counter A clock source selection
— Counter A interrupt enable/disable
— Counter A interrupt pending control (read for status, write to clear)
— Counter A interrupt time selection
Counter A Control Register (CACON)
F3H, Set 1, Bank 0, R/W
.7 .6 .5 .4 .3 .2 .1 .0 MSB LSB
Counter A Output Flip-Flop Control Bit(CAOF):
0 = T-F/F is low
1 = T-F/F is high
Counter A Mode Selection Bit:
0 = One shot mode
1 = Repeating mode
Counter A Start/Stop Bit:
0 = Stop counter A
1 = Start counter A
Counter A Input Clock Selection Bits:
00 = f
OSC
01 = f
OSC
/2
10 = f
OSC
/4
11 = f
OSC
/8
Counter A Interrupt Enable Bit:
0 = Disable interrupt
1 = Enable interrupt
Counter A Interrupt Time Selection Bits:
00 = Elapsed time for low data value
01 = Elapsed time for high data value
10 = Elapsed time for low and high data values
11 = Invalid setting
Figure 12-2. Counter A Control Register (CACON)
Counter A Data High-Byte Register (CADATAH)
F4H, Set 1, Bank 0, R/W
.7 .6 .5 .4 .3 .2 .1 .0 MSB LSB
Reset Value: FFH
Counter A Data Low-Byte Register (CADATAL)
F5H, Set 1, Bank 0, R/W
.7 .6 .5 .4 .3 .2 .1 .0 MSB LSB
Reset Value: FFH
Figure 12-3. Counter A Registers
12-3