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Samsung S3F80P5X, User Manual

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INTERRUPT STRUCTURE 

 

S3F80P5_UM_ REV1.00 

INTERRUPT MASK REGISTER (IMR) 

The interrupt mask register, IMR (DDH, Set 1, and Bank0) is used to enable or disable interrupt processing for 
individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their 
required settings by the initialization routine. 

Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit of 
an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a level's 
IMR bit to "1", interrupt processing for the level is enabled (not masked). 

The IMR register is mapped to register location DDH in set 1and Bank0. Bit values can be read and written by 
instructions using the register addressing mode.  

 

NOTE:

Before IMR register is changed to any value, all interrupts must be disable.
Using DI instruction is recommended.

DDH, Set 1, Bank 0, R/W

Interrupt Mask Register (IMR)

.7

.6

.5

.4

.3

.2

.1

.0

MS

B

LSB

IRQ

1

IRQ

2

IRQ

3

IRQ

4

IRQ

6

IRQ

7

IRQ

0

0 = Disable (mask) interrupt
1 = Enable (un-mask) interrupt

Not

used

Interrupt Level Enable Bits (7-0):

 

 

Figure 5-6. Interrupt Mask Register (IMR) 

5-10  

 

Summary of Contents for S3F80P5X

Page 1: ...USER S MANUAL S3F80P5X S3F80P5 MICROCONTROLLERS April 2010 REV 1 00 Confidential Proprietary of Samsung Electronics Co Ltd Copyright 2009 Samsung Electronics Inc All Rights Reserved ...

Page 2: ...ions intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmle...

Page 3: ...rity with the information in Part I will help you to understand the hardware module descriptions in Part II If you are not yet familiar with the S3FS series microcontroller family and are reading this manual for the first time we recommend that you first read Chapters 1 3 carefully Then you can reference the information in Part II as necessary Part II hardware Descriptions has detailed information...

Page 4: ...s 1 2 Block Diagram 24 pin package 1 3 Pin Assignments 1 4 Pin Circuits 1 6 Chapter 2 Address Spaces Overview 2 1 Program Memory 2 2 Smart Option 2 3 Register Architecture 2 5 Register Page Pointer PP 2 7 Register Set 1 2 8 Register Set 2 2 8 Prime Register Space 2 9 Working Registers 2 10 Using the Register Pointers 2 11 Register Addressing 2 13 Common Working Register Area C0H CFH 2 15 Example 1...

Page 5: ...rs 5 6 Interrupt Processing Control Points 5 7 Peripheral Interrupt Control Registers 5 8 System Mode Register SYM 5 9 Interrupt Mask Register IMR 5 10 Interrupt Priority Register IPR 5 11 Interrupt Request Register IRQ 5 13 Interrupt Pending Function Types 5 14 Overview 5 14 Pending Bits Cleared Automatically by Hardware 5 14 Pending Bits Cleared by the Service Routine 5 14 Interrupt Source Polli...

Page 6: ...erview 8 1 Reset Sources 8 1 Reset Mechanism 8 4 Watch dog timer Reset 8 4 LVD Reset 8 4 Internal Power On Reset 8 5 External Interrupt Reset 8 6 Stop Error Detection Recovery 8 7 Power Down Modes 8 8 Idle Mode 8 8 IDLE Mode Release 8 8 Back up Mode 8 9 Stop Mode 8 11 Sources to Release Stop Mode 8 12 Using IPOR to Release Stop Mode 8 12 Using an External Interrupt to Release Stop Mode 8 12 SED R ...

Page 7: ...Description 10 3 Watch dog Timer Function 10 3 Oscillation Stabilization Interval Timer Function 10 3 Timer 0 Control Register T0CON 10 4 Timer 0 Function Description 10 6 Timer 0 Interrupts IRQ0 Vectors FAH and FCH 10 6 Interval Timer Mode 10 6 Pulse Width Modulation Mode 10 7 Capture Mode 10 8 Chapter 11 Timer 1 Overview 11 1 Timer 1 Overflow Interrupt 11 2 Timer 1 Capture Interrupt 11 2 Timer 1...

Page 8: ... ISPTM On Board Programming SECTOR 14 2 Smart Option 14 3 ISP Reset Vector and ISP Sector Size 14 4 Flash Memory Control Registers User Program Mode 14 5 Flash Memory Control Register FMCOn 14 5 Flash Memory User Programming Enable Register FMUSR 14 5 Flash Memory Sector Address Registers 14 6 Sector Erase 14 7 The Sector Erase Procedure in User Program Mode 14 8 Programming 14 11 The Program Proc...

Page 9: ...echanical 17 1 Overview 17 1 Chapter 18 S3F80P5 Flash MCU Overview 18 1 Operating Mode Characteristics 18 4 Chapter 19 Development Tools Overview 19 1 Target Boards 19 1 Programming Socket Adapter 19 1 TB80PB Target Board 19 3 Third Parties for Development Tools 19 7 In Circuit Emulator for SAM8 Family 19 7 OTP MTP Programmer 19 7 Development Tools Suppliers 19 7 8 bit In Circuit Emulator 19 7 OTP...

Page 10: ......

Page 11: ...rking Register Addressing 2 17 2 13 4 Bit Working Register Addressing Example 2 17 2 14 8 Bit Working Register Addressing 2 18 2 15 8 Bit Working Register Addressing Example 2 19 2 16 Stack Operations 2 20 3 1 Register Addressing 3 2 3 2 Working Register Addressing 3 2 3 3 Indirect Register Addressing to Register File 3 3 3 4 Indirect Register Addressing to Program Memory 3 4 3 5 Indirect Working ...

Page 12: ...iming Diagram for Internal Power On Reset Circuit 8 5 8 5 Reset Timing Diagram for the S3F80P5 in Stop Mode by IPOR 8 6 8 6 Block Diagram for Back up Mode 8 9 8 7 Timing Diagram for Back up Mode Input and Released by LVD 8 9 8 8 Timing Diagram for Back up Mode Input in Stop Mode 8 10 9 1 S3F80P5 I O Port Data Register Format 9 3 9 2 Pull up Resistor Enable Registers Port 0 and Port2 9 4 10 1 Basic...

Page 13: ...figurations in User Program Mode 14 7 14 8 Sector Erase Flowchart in User Program Mode 14 8 14 9 Byte Program Flowchart in a User Program Mode 14 12 14 10 Program Flowchart in a User Program Mode 14 13 15 1 Low Voltage Detect LVD Block Diagram 15 3 15 2 Low Voltage Detect Control Register LVDCON 15 4 15 3 Low Voltage Detect Flag Selection Register LVDSEL 15 4 16 1 Stop Mode Release Timing When Ini...

Page 14: ......

Page 15: ...in Stop Mode 8 7 8 2 Set 1 Bank 0 Register Values After Reset 8 15 8 3 Set 1 Bank 1 Register Values After Reset 8 17 8 4 Reset Generation According to the Condition of Smart Option 8 18 8 5 Guideline for Unused Pins to Reduced Power Consumption 8 19 8 6 Summary of Each Mode 8 20 9 1 S3F80P5 Port Configuration Overview 24 SOP 9 2 9 2 Port Data Register Summary 9 3 14 1 ISP Sector Size 14 4 14 2 Res...

Page 16: ...Page Number Number 18 1 Descriptions of Pins Used to Read Write the Flash ROM 18 3 18 2 Operating Mode Selection Criteria 18 4 19 1 Components of TB80PB 19 4 19 2 Setting of the Jumper in TB80PB 19 5 xvi S3F80P5_UM_REV1 00 MICROCONTROLLER ...

Page 17: ...CROCONTROLLER The S3F80P5 single chip CMOS microcontroller is fabricated using a highly advanced CMOS process and is based on Samsung s newest CPU architecture The S3F80P5 is the microcontroller which has 18 Kbyte Flash Memory ROM Using a proven modular design approach Samsung engineers developed S3F80P5 by integrating the following peripheral modules with the powerful SAM8 RC core Internal LVD ci...

Page 18: ...ntrol or watchdog timer software reset function One 8 bit timer counter Timer 0 with three operating modes Interval mode Capture and PWM mode One 16 bit timer counter Timer1 with two operating modes Interval and Capture mode One 16 bit timer counter Timer2 with two operating modes Interval and Capture mode Back up Mode When VDD is lower than VLVD LVD is ON and the chip enters Back up mode to block...

Page 19: ...S3F80P5_UM_ REV1 00 PRODUCT OVERVIEW BLOCK DIAGRAM 24 PIN PACKAGE Figure 1 1 Block Diagram 24 pin 1 3 ...

Page 20: ...P0 2 INT2 P0 3 INT3 P0 4 INT4 P0 5 INT4 P0 6 INT4 P0 7 INT4 S3C80P5 24 SOP SDIP TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 12 VDD P2 0 INT5 P3 1 REM T0CK P3 0 T0PWM T0CAP T1CAP T2CAP P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 24 23 22 21 20 19 18 17 16 15 14 13 Figure 1 2 Pin Assignment Diagram 24 Pin SOP SDIP Package 1 4 ...

Page 21: ... can be assigned as external interrupt input with noise filter interrupt enable disable and interrupt pending control 3 23 Ext INT INT5 P3 0 I O I O port with bit programmable pin Configurable to input mode push pull output mode or n channel open drain output mode Input mode with a pull up resistor can be assigned by software This port 3 pin has high current drive capability Also P3 0 can be assig...

Page 22: ...VIEW S3F80P5_UM_ REV1 00 PIN CIRCUITS VDD Pull up Enable VDD INPUT OUTPUT Pull Up Resistor 67kΩ typ Data VSS External Interrupt Output Disable Noise Filter Stop Stop Release Figure 1 3 Pin Circuit Type 1 Port 0 1 6 ...

Page 23: ... REV1 00 PRODUCT OVERVIEW PIN CIRCUITS Continued VDD Pull up Resistor 67kΩ Typ VDD VSS Noise Filter INPUT OUTPUT Pull up Enable Data Output Disable Normal Input Open Drain Figure 1 4 Pin Circuit Type 2 Port 1 1 7 ...

Page 24: ...EW S3F80P5_UM_ REV1 00 PIN CIRCUITS Continued Data Output Disable Open Drain VDD Pull up Enable VDD INPUT OUTPUT Pull Up Resistor 67kΩ typ VSS External Interrupt Noise Filter Figure 1 5 Pin Circuit Type 2 Port 2 1 8 ...

Page 25: ...ntinued VDD Pull up Enable P3 0 T0PWM T0CAP T1CAP T2CAP Pull up Resistor 67kΩ Typ Open Drain Port 3 0 Data VSS P3 0 Input M U X P3CON 2 Data Output Disable T0CAP T1CAP T2CAP T0_PWM Noise filter M U X P3CON 2 6 7 VDD Figure 1 6 Pin Circuit Type 4 P3 0 1 9 ...

Page 26: ...ontinued VDD Pull up Enable VDD P3 1 REM T0CK Pull up Resistor 67kΩ Typ Open Drain Port 3 1 Data VSS P3 1 Input M U X P3CON 5 Data Output Disable T0CK Carrier On Off P3DAT 7 CACON 2 Noise filter M U X P3CON 5 6 7 Figure 1 7 Pin Circuit Type 5 P3 1 1 10 ...

Page 27: ... has a programmable internal 18 Kbytes Flash ROM An external memory interface is not implemented There are 333 mapped registers in the internal register file Of these 272 byte are for general purpose use This number includes a 16 byte working register common area that is used as a scratch area for data operations a 192 byte prime register area and a 64 byte area Set 2 that is also used for stack o...

Page 28: ...hese locations The program memory address at which program execution starts after reset is 0100H default If you use ISPTM sectors as the ISPTM software storage the reset vector address can be changed by setting the Smart Option Refer to Figure 2 2 Internal Program Memory Flash 1 Kbyte Internal RAM Interrupt Vector Area ISP Sector Smart Option Rom Cell 65 536 255 0 00H 0FFH FC00H FFFFH 01FFH 02FFH ...

Page 29: ...03FH RESET Control Bit 0 External interrupts by P0 and P2 or SED R generate the reset signal 1 External interrupts by P0 and P2 or SED R do not generate the reset signal ISP Reset Vector Address Selection Bits 2 00 200H ISP Area size 256 bytes 01 300H ISP Area size 512 bytes 10 500H ISP Area size 1024 bytes 11 900H ISP Area size 2048 bytes ROM Address 003EH ISP Protection Size Selection Bits 4 00 ...

Page 30: ...SP area can be assigned from 0100H to 04FFH 1024bytes If 0900H the ISP area can be assigned from 0100H to 08FFH 2048bytes 3 If ISP Protection Enable Disable Bit is 0 user can t erase or program the ISP area selected by 3EH 1 and 3EH 0 in flash memory 4 User can select suitable ISP protection size by 3EH 1 and 3EH 0 If ISP Protection Enable Disable Bit 3EH 2 is 1 3EH 1 and 3EH 0 are meaningless 5 E...

Page 31: ...ed as shared working registers and 272 registers are for general purpose use The extension of register space into separately addressable areas sets banks is supported by various addressing mode restrictions the select bank instructions SB0 and SB1 Specific register types and the area occupied in the S3F80P5 internal register space are summarized in Table 2 1 Table 2 1 The Summary of S3F80P5 Regist...

Page 32: ...ter Addressing Mode Working Register Working Register Addressing only FFH Set 1 FFH Set 2 C0H Page 0 General Purpose Data Register Indirect Register or Indexed Addressing Modes or Stack Operations 256 Bytes E0H Page 0 Prime Data Register All Addressing Mode BFH 192 Bytes 00H 64 Bytes 32 Bytes 32 Bytes Figure 2 3 Internal Register File Organization 2 6 ...

Page 33: ...ter s source value lower nibble and destination value upper nibble are always 0000 automatically Therefore S3F80P5 is always selected page 0 as the source and destination page for register addressing These page pointer PP register settings as shown in Figure 2 4 should not be modified during normal operation NOTE A hardware reset operation writes the 4 bit destination and source values shown above...

Page 34: ...CFH You can use the common working register area as a scratch area for data operations being performed in other areas of the register file Registers in set 1 locations are directly accessible at all times using the Register addressing mode The 16 byte working register area can only be accessed using working register addressing For more information about working register addressing please refer to ...

Page 35: ...ess using any addressing mode In other words there is no addressing mode restriction for these registers as is the case for set 1 and set 2 registers The prime register area on page 0 is immediately addressable following a reset FFH FCH E0H D0H C0H Bank 0 FFH C0H Set 2 00H Prime Register Area Peripheral and IO General purpose CPU and system control Set 1 Bank 1 Page 0 Page 0 BFH Figure 2 5 Set 1 S...

Page 36: ...e locations of selected working register spaces One working register slice is 8 bytes eight 8 bit working registers R0 R7 or R8 R15 One working register block is 16 bytes sixteen 8 bit working registers R0 R15 All of the registers in an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possible for each register pointer to point to ...

Page 37: ...ed 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline we recommend that RP0 point to the lower slice and RP1 point to the upper slice see Figure 2 6 In some cases it may be necessary to define working register areas in different non contiguous areas of the register file In Figure 2 7 RP0 points to the upper slice and RP1 to the lower ...

Page 38: ...0 R1 ADC R0 R2 R0 R0 R2 C ADC R0 R3 R0 R0 R3 C ADC R0 R4 R0 R0 R4 C ADC R0 R5 R0 R0 R5 C The sum of these six registers 6FH is located in the register R0 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence would have to be...

Page 39: ... 8 bit register within that space Registers are addressed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the first 8 bit register is always an even number and the address of the next register is always an odd number The most significant byte of the 16 bit data is always stored in the even numbered register the least significant byte ...

Page 40: ...r Each register pointer RP can independently point to one of the 24 8 byte slices of the register file other than set 2 After a reset RP0 points to locations C0H C7H and RP1 to locations C8H CFH that is to the common working register area Control Registers System Registers Bank 1 Prime Registers NOTE In the S3F80K5 microcontroller only page0 is implemented Page0 containsall of the addressable regi...

Page 41: ...on area That is locations in this area can be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations 0 Following a hareware reset register pointers RP0 and RP1 point to the common working register area locations C0H CFH FFH F0H C0H Set 1 FFH BFH Set 2 00H Prime Area RP0 RP1 ...

Page 42: ...the address bits are concatenated in the following way to form a complete 8 bit address The high order bit of the 4 bit address selects one of the register pointers 0 selects RP0 1 selects RP1 The five high order bits in the register pointer select an 8 byte slice of the register space The three low order bits of the 4 bit address select one of the eight registers in the slice As shown in Figure 2...

Page 43: ...ts Address OPCODE Selects RP0 or RP1 RP1 RP0 4 bit address procides three low order bits Figure 2 12 4 Bit Working Register Addressing Register address 76H RP0 R6 Selects RP0 Instruction INC R6 OPCODE RP1 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 0 0 1 1 1 0 0 0 1 0 1 1 0 1 1 1 0 Figure 2 13 4 Bit Working Register Addressing Example 2 17 ...

Page 44: ... address are provided by the original instruction Figure 2 14 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 4 1 selects RP1 and the five high order bits in RP1 10101B become the five high order bits of the register address The three low order bits of the register address 011 are provided...

Page 45: ...ies working register addressing RP0 Selects RP1 RP1 0 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 Register address 0ABH 0 1 1 0 1 1 1 0 8 bit address from instruction LD R11 R2 R11 Figure 2 15 8 Bit Working Register Addressing Example 2 19 ...

Page 46: ...stack address value is always decreased by one before a push operation and increased by one after a pop operation The stack pointer SP always points to the stack frame stored on the top of the stack as shown in Figure 2 15 Stack contents after a call instruction Stack contents after an interrupt Top of stack Flags PCH PCL PCL PCH Top of stack Low Address High Address Figure 2 16 Stack Operations U...

Page 47: ...register file using PUSH and POP instructions LD SPL 0FFH SPL FFH Normally the SPL is set to 0FFH by the initialization routine PUSH PP Stack address 0FEH PP PUSH RP0 Stack address 0FDH RP0 PUSH RP1 Stack address 0FCH RP1 PUSH R3 Stack address 0FBH R3 POP R3 R3 Stack address 0FBH POP RP1 RP1 Stack address 0FCH POP RP0 RP0 Stack address 0FDH POP PP PP Stack address 0FEH 2 21 ...

Page 48: ...ADDRESS SPACE S3F80P5_UM_ REV1 00 NOTES 2 22 ...

Page 49: ...the method used to determine the location of the data operand The operands specified in instructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C8 S3F8 series instruction set supports seven explicit addressing modes Not all of these addressing modes are available for each instruction Register R Indirect Register IR Indexed X Direct ...

Page 50: ...OPERAND 8 bit register file address Points to one register in register file One Operand Instruction Example Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Program Memory Register File Figure 3 1 Register Addressing dst OPCODE 4 bit Working Register Points to the woking register 1 of 8 Two Operand Instruction Example Sample Instruction ADD R1 R2 Where R1 and R2 are...

Page 51: ...t register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Remember however that locations C0H FFH in set 1 cannot be accessed using Indirect Register addressing mode dst Address of operand used by instruction OPCODE ADDRESS 8 bit register file address Points to one register in register file One Operand Instruction Example S...

Page 52: ...nts to Register Pair Example Instruction References Program Memory Sample Instructions CALL RR2 JP RR2 Program Memory Register File Value used in instruction OPERAND Register Pair Program Memory 16 Bit Address Points to Program Memory Figure 3 4 Indirect Register Addressing to Program Memory 3 4 ...

Page 53: ...g Register Address Point to the Woking Register 1 of 8 Sample Instruction OR R3 R6 Program Memory Register File src 3 LSBs Value used in instruction OPERAND Selected RP points to start of woking register block RP0 or RP1 MSB Points to RP0 or RP1 Figure 3 5 Indirect Working Register Addressing to Register File 3 5 ...

Page 54: ...uction OPERAND Example Instruction References either Program Memory or Data Memory Program Memory or Data Memory Next 2 bit Point to Working Register Pair 1 of 4 LSB Selects 16 Bit address points to program memory or data memory RP0 or RP1 MSB Points to RP0 or RP1 Selected RP points to start of working register block NOTE LDE command is not available because an external interface is not implemente...

Page 55: ...it offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to the base address see Figure 3 9 The only instruction that supports indexed addressing mode for the internal register file is the Load instruction LD The LDC and LDE instructi...

Page 56: ...ructions LDC R4 04H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 04H RR2 Identical operation to LDC example except that external data memory is accessed NEXT 2 BITS Register Pair Value used in Instruction 8 Bit 16 Bit 16 Bit dst src OPCODE Program Memory x OFFSET 4 bit Working Register Address NOTE LDE command is not available because an external interface is no...

Page 57: ...ctions LDC R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external data memory is accessed NEXT 2 BITS Register Pair Value used in Instruction 16 Bit 16 Bit 16 Bit dst src OPCODE Program Memory x OFFSET 4 bit Working Register Address OFFSET NOTE LDE command is not available because an external int...

Page 58: ...or Load operations to program memory LDC or to external data memory LDE if implemented Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H Identical operation to LDC example except that external data memory is accessed dst src OPCODE Program Memory 0 or 1 Lower Address Byte LSB Selects Program Memory or Data Memory 0 Program Memory 1 Da...

Page 59: ...am Memory Lower Address Byte Program Memory Address Used Upper Address Byte Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Next OPCODE Figure 3 11 Direct Addressing for Call and Jump Instructions 3 11 ...

Page 60: ...mode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Current Instruction Program Memory Locations 0 255 Program Memory OPCODE dst Lower Address Byte Upper Address Byte Next Instruction LSB Must be Zero Sample Ins...

Page 61: ...rs the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing are BTJRF BTJRT DJNZ CPIJE CPIJNE and JR OPCODE Program Memory Displacement Program Memory Address Used Sample Instructions JR ULT OFFSET Where OFFSET is a value in...

Page 62: ...pplied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers The operand value is in the instruction OPCODE Sample Instruction LD R0 0AAH Program Memory OPERAND Figure 3 14 Immediate Addressing 3 14 ...

Page 63: ... register description format Control register descriptions are arranged in alphabetical order A Z according to the register mnemonic More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part II of this manual Data and counter registers are not described in detail in this reference section More information about all of the...

Page 64: ... System Mode Register SYM 222 DEH R W Register Page Pointer PP 223 DFH R W Port 0 Data Register P0 224 E0H R W Port 1 Data Register P1 225 E1H R W Port 2 Data Register P2 226 E2H R W Port 3 Data Register P3 227 E3H R W Reserved E4H Port 2 Interrupt Enable Register P2INT 229 E5H R W Port 2 Interrupt Pending Register P2PND 230 E6H R W Port 0 Pull up Resistor Enable Register P0PUR 231 E7H R W Port 0 ...

Page 65: ... F6H R NOTE Timer 1 Counter Register Low Byte T1CNTL 247 F7H R NOTE Timer 1 Data Register High Byte T1DATAH 248 F8H R W Timer 1 Data Register Low Byte T1DATAL 249 F9H R W Timer 1 Control Register T1CON 250 FAH R W STOP Control Register STOPCON 251 FBH W Location FCH is not mapped Basic Timer Counter BTCNT 253 FDH R NOTE External Memory Timing Register EMT 254 FEH R W Interrupt Priority Register IP...

Page 66: ...AH is not mapped Location EBH is not mapped Flash Memory Sector Address Register High Byte FMSECH 236 EC R W Flash Memory Sector Address Register Low Byte FMSECL 237 ED R W Flash Memory User Programming Enable Register FMUSR 238 EE R W Flash Memory Control Register FMCON 239 EF R W Reset Indicating Register RESETID 240 F0 R W LVD Flag Selection Register LVDSEL 243 F1 R W PORT1 Output Mode Pull up ...

Page 67: ... name for bit addressing D5H Register address Hexadecimal Full register name Register mnemonic Name of individual bit or bit function 7 6 5 4 2 3 1 0 x R W x R W x R W x R W 0 R W x R W 0 R W x R W Zero Flag Bit Z 0 Operation result is a non zero value 1 Operation result is zero Sign Flag Bit S 0 Operation generates positive number MSB 0 1 Operation generates negative number MSB 1 7 Carry Flag Bit...

Page 68: ...ion Bits 0 0 fOSC 4096 0 1 fOSC 1024 1 0 fOSC 128 1 1 fOSC 16384 1 Basic Timer Counter Clear Bit 1 0 No effect 1 Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for Basic Timer and Timer 0 2 0 No effect 1 Clear both block frequency dividers NOTES 1 When you write a 1 to BTCON 1 the basic timer counter value is cleared to 00H Immediately following the write operation the BTC...

Page 69: ...1 fOSC 8 5 and 4 Counter A Interrupt Timing Selection Bits 0 0 Elapsed time for Low data value 0 1 Elapsed time for High data value 1 0 Elapsed time for combined Low and High data values 1 1 Not used for S3F80P5 3 Counter A Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt 2 Counter A Start Bit 0 Stop counter A 1 Start counter A 1 Counter A Mode Selection Bit 0 One shot mode 1 Repeating ...

Page 70: ...fOSC 8 1 0 fOSC 2 1 1 fOSC non divided 2 0 Subsystem Clock Selection Bits 2 1 0 1 Not used for S3F80P5 Other value Select main system clock MCLK NOTES 1 After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate values to CLKCON 3 and CLKCON 4 2 These selection bits CLKCON 0 1 2 are required only for systems that have a main clo...

Page 71: ...g 5 and 4 Program Memory Automatic Wait Control Bits 0 0 No wait 0 1 Wait one cycle 1 0 Wait two cycles 1 1 Wait three cycles 3 and 2 Data Memory Automatic Wait Control Bits 0 0 No wait 0 1 Wait one cycle 1 0 Wait two cycles 1 1 Wait three cycles 1 Stack Area Selection Bit 0 Select internal register file area 1 Select external data memory area 0 Not used for S3F80P5 NOTE The EMT register is not us...

Page 72: ... 0 Operation generates a positive number MSB 0 1 Operation generates a negative number MSB 1 4 Overflow Flag Bit V 0 Operation result is 127 or 128 1 Operation result is 127 or 128 3 Decimal Adjust Flag Bit D 0 Add operation completed 1 Subtraction operation completed 2 Half Carry Flag Bit H 0 No carry out of bit 3 or no borrow into bit 3 by addition or subtraction 1 Addition generated carry out o...

Page 73: ...e Register addressing mode only 7 4 Flash Memory Mode Selection Bits 0101 Programming mode 1010 Erase mode 0110 Hard Lock mode NOTE Others Not used for S3F80P5 3 1 Not used for S3F80P5 0 Flash Operation Start Bit available for Erase and Hard Lock mode only 0 Operation stop 1 Operation start auto clear bit NOTE Hard Lock mode is one of the flash protection modes Refer to page 13 17 4 11 ...

Page 74: ...Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Flash Memory Sector Address Low Byte Note The low byte flash memory sector address pointer value is the lower eight bits of the 16 bit pointer address FMUSR Flash Memory User Programming Enable Register EEH Set1 Bank1 Bit Identifier 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W ...

Page 75: ...e Bit External Interrupts P0 3 P0 0 0 Disable mask 1 Enable un mask 5 Not used for S3F80P5 4 Interrupt Level 4 IRQ4 Enable Bit External Interrupts P2 0 0 Disable mask 1 Enable un mask 3 Interrupt Level 3 IRQ3 Enable Bit Timer 2 Match or Overflow 0 Disable mask 1 Enable un mask 2 Interrupt Level 2 IRQ2 Enable Bit Counter A Interrupt 0 Disable mask 1 Enable un mask 1 Interrupt Level 1 IRQ1 Enable Bi...

Page 76: ... of the 16 bit instruction pointer address IP15 IP8 The lower byte of the IP address is located in the IPL register DBH IPL Instruction Pointer Low Byte DBH Set1 Bank0 Bit Identifier 7 6 5 4 3 2 1 0 Reset Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address Low Byte The low byte instruction pointer value is t...

Page 77: ...ined 0 0 1 B C A 0 1 0 A B C 0 1 1 B A C 1 0 0 C A B 1 0 1 C B A 1 1 0 A C B 1 1 1 Group priority undefined 6 Interrupt Subgroup C Priority Control Bit 0 IRQ6 IRQ7 1 IRQ7 IRQ6 5 Not used for S3F80P5 3 Interrupt Subgroup B Priority Control Bit See Note 0 IRQ3 IRQ4 1 IRQ4 IRQ3 2 Interrupt Group B Priority Control Bit See Note 0 IRQ2 IRQ3 IRQ4 1 IRQ3 IRQ4 IRQ2 0 Interrupt Group A Priority Control Bit...

Page 78: ...ding Bit External Interrupts P0 3 P0 0 0 Not pending 1 Pending 5 Not used for S3F80P5 4 Level 4 IRQ4 Request Pending Bit External Interrupts P2 0 0 Not pending 1 Pending 3 Level 3 IRQ3 Request Pending Bit Timer 2 Match Capture or Overflow 0 Not pending 1 Pending 2 Level 2 IRQ2 Request Pending Bit Counter A Interrupt 0 Not pending 1 Pending 1 Level 1 IRQ1 Request Pending Bit Timer 1 Match Capture o...

Page 79: ... Value 0 Read Write R W Addressing Mode Register addressing mode only 7 1 Not used for S3F80P5 0 LVD Flag Indicator Bit 0 VDD LVD_FLAG Level 1 VDD LVD_FLAG Level NOTE When LVD detects LVD_FLAG level LVDCON 0 flag bit is set automatically When VDD is upper LVD_FLAG level LVDCON 0 flag bit is cleared automatically 4 17 ...

Page 80: ...1 Bank1 Bit Identifier 7 6 5 4 3 2 1 0 Reset Value 0 0 Read Write R W R W Addressing Mode Register addressing mode only 7 and 6 LVD Flag Level Selection Bits 0 0 LVD_FLAG Level 1 88V 0 1 LVD_FLAG Level 1 98V 1 0 LVD_FLAG Level 2 53V 1 1 LVD_FLAG Level 2 73V 5 0 Not used for S3F80P5 4 18 ...

Page 81: ...d falling edges 1 0 Push pull output mode 1 1 C MOS input mode interrupt on rising edges 3 and 2 P0 5 INT4 Mode Selection Bits 0 0 C MOS input mode interrupt on falling edges 0 1 C MOS input mode interrupt on rising and falling edges 1 0 Push pull output mode 1 1 C MOS input mode interrupt on rising edges 1 and 0 P0 4 INT4 Mode Selection Bits 0 0 C MOS input mode interrupt on falling edges 0 1 C M...

Page 82: ...nd falling edges 1 0 Push pull output mode 1 1 C MOS input mode interrupt on rising edges 3 and 2 P0 1 INT1 Mode Selection Bits 0 0 C MOS input mode interrupt on falling edges 0 1 C MOS input mode interrupt on rising and falling edges 1 0 Push pull output mode 1 1 C MOS input mode interrupt on rising edges 1 and 0 P0 0 INT0 Mode Selection Bits 0 0 C MOS input mode interrupt on falling edges 0 1 C ...

Page 83: ...rrupt INT4 Enable Bit 0 Disable interrupt 1 Enable interrupt 5 P0 5 External Interrupt INT4 Enable Bit 0 Disable interrupt 1 Enable interrupt 4 P0 4 External Interrupt INT4 Enable Bit 0 Disable interrupt 1 Enable interrupt 3 P0 3 External Interrupt INT3 Enable Bit 0 Disable interrupt 1 Enable interrupt 2 P0 2 External Interrupt INT2 Enable Bit 0 Disable interrupt 1 Enable interrupt 1 P0 1 External...

Page 84: ...en read 4 P0 4 External Interrupt INT4 Pending Flag Bit 0 No P0 4 external interrupt pending when read 1 P0 4 external interrupt is pending when read 3 P0 3 External Interrupt INT3 Pending Flag Bit 0 No P0 3 external interrupt pending when read 1 P0 3 external interrupt is pending when read 2 P0 2 External Interrupt INT2 Pending Flag Bit 0 No P0 2 external interrupt pending when read 1 P0 2 extern...

Page 85: ...le pull up resistor 1 Enable pull up resistor 5 P0 5 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 4 P0 4 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 3 P0 3 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 2 P0 2 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 1 ...

Page 86: ... P1 6 Mode Selection Bits 0 0 C MOS input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 C MOS input with pull up mode 3 and 2 P1 5 Mode Selection Bits 0 0 C MOS input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 C MOS input with pull up mode 1 and 0 P1 4 Mode Selection Bits 0 0 C MOS input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 C MOS input wi...

Page 87: ...drain output mode 1 0 Push pull output mode 1 1 C MOS input with pull up mode 5 and 4 P1 2 Mode Selection Bits 0 0 C MOS input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 C MOS input with pull up mode 3 and 2 P1 1 Mode Selection Bits 0 0 C MOS input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 C MOS input with pull up mode 1 and 0 P1 0 Mode Selection Bits 0 0 C M...

Page 88: ... 1 Enable pull up resistor 5 P1 5 Output Mode Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 4 P1 4 Output Mode Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 3 P1 3 Output Mode Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 2 P1 2 Output Mode Pull up Resistor Enable Bit 0 Disable pull up resistor...

Page 89: ... mode only 1 and 0 P2 0 INT5 Mode Selection Bits 0 0 C MOS input mode interrupt on falling edges 0 1 C MOS input mode interrupt on rising edges and falling edges 1 0 Output mode push pull or open drain output refer to P2OUTMD 1 1 C MOS input mode interrupt on rising edges NOTE Pull up resistors can be assigned to individual port 2 pins by making the appropriate settings to the P2PUR control regist...

Page 90: ...upt Enable Register E5H Set1 Bank0 Bit Identifier 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 0 P2 0 External Interrupt INT4 Enable Bit 0 Disable interrupt 1 Enable interrupt 4 28 ...

Page 91: ...election Register F3H Set1 Bank1 Bit Identifier 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 0 P2 0 Output Mode Selection Bit 0 Push pull output mode 1 Open drain output mode 4 29 ...

Page 92: ... R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 0 P2 0 External Interrupt INT4 Pending Flag Bit 0 No P2 0 external interrupt pending when read 1 P2 0 external interrupt is pending when read NOTE To clear an interrupt pending condition write a 0 to the appropriate pending flag bit Writing a 1 to an interrupt rending flag P2PND 0 7 has no effect 4 30 ...

Page 93: ...nable Register EEH Set1 Bank0 Bit Identifier 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 0 P2 0 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 4 31 ...

Page 94: ... Not used for S3F80P5 5 P3 1 Function Selection Bit 0 Normal I O selection 1 Alternative function enable REM T0CK 4 and 3 P3 1 Mode Selection Bits 0 0 Schmitt trigger input mode 0 1 Open drain output mode 1 0 Push pull output mode 1 1 Schmitt trigger input with pull up resistor 2 Function Selection Bit for P3 0 0 Normal I O selection 1 Alternative function enable P3 0 T0PWM T0CAP T1CAP 1 and 0 P3 ...

Page 95: ...ding to the each bit control of P3CON in 24 pin package Table 4 3 Each Function Description and Pin Assignment of P3CON in 24 Pin Package P3CON Each Function Description and Assignment to P3 0 P3 3 B5 B4 B3 B2 B1 B0 P3 0 P3 1 0 x x 0 x x Normal I O Normal I O 0 x x 1 0 0 T0_CAP T1_CAP Normal I O 0 x x 1 1 1 T0_CAP T1_CAP Normal I O 0 x x 1 0 1 T0PWM Normal I O 0 x x 1 1 0 T0PWM Normal I O 1 0 0 0 ...

Page 96: ... 5 4 3 2 1 0 Reset Value 0 0 Read Write R W R W Addressing Mode Register addressing mode only 7 and 2 Not used for S3F80P5 1 P3 1 Output Mode Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 0 P3 0 Output Mode Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 4 34 ...

Page 97: ...tion Bits 0 0 0 0 Destination page 0 See Note 3 0 Source Register Page Selection Bits 0 0 0 0 Source page 0 See Note NOTE In the S3F80P5 microcontroller a paged expansion of the internal register file is not implemented For this reason only page 0 settings are valid Register page pointer values for the source and destination register page are automatically set to 0000B following a hardware reset T...

Page 98: ...Reset is generated by WDT when read 1 LVD Reset Indicating Bit 0 Reset is not generated by LVD when read 1 Reset is generated by LVD when read 0 POR Reset Indicating Bit 0 Reset is not generated by POR when read 1 Reset is generated by POR when read State of RESETID depends on reset source 7 6 5 4 3 2 1 0 POR 0 0 0 1 1 LVD 0 0 0 1 note2 WDT Key in note3 note2 NOTES 1 To clear an indicating registe...

Page 99: ...s to address C0H in register set 1 bank0 selecting the 8 byte working register slice C0H C7H 2 0 Not used for S3F80P5 RP1 Register Pointer 1 D7H Set1 Bank0 Bit Identifier 7 6 5 4 3 2 1 0 Reset Value 1 1 0 0 1 Read Write R W R W R W R W R W Addressing Mode Register addressing mode only 7 3 Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 248 byte working reg...

Page 100: ...Stop Control Register FBH Set1 Bank0 Bit Identifier 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 0 0 Read Write W W W W W W W W Addressing Mode Register addressing mode only 7 0 Stop Control Register Enable Bits 1 0 1 0 0 1 0 1 Enable STOP Mode Other value Disable STOP Mode NOTES 1 To get into STOP mode stop control register must be enabled just before STOP instruction 2 When STOP mode is released stop...

Page 101: ...rupt Enable Bit note4 0 Disable fast interrupt processing 1 Enable fast interrupt processing 0 Global Interrupt Enable Bit note5 0 Disable global interrupt processing 1 Enable global interrupt processing NOTES 1 Because an external interface is not implemented for the S3F80P5 SYM 7 must always be 0 2 Although the SYM register is not used SYM 5 should always be 0 If you accidentally write a 1 to th...

Page 102: ...r 1 1 PWM mode Match and OVF interrupt can occur 3 Timer 0 Counter Clear Bit 0 No effect when write 1 Clear T0 counter T0CNT when write 2 Timer 0 Overflow Interrupt Enable Bit note 0 Disable T0 overflow interrupt 1 Enable T0 overflow interrupt 1 Timer 0 Match Capture Interrupt Enable Bit 0 Disable T0 match capture interrupt 1 Enable T0 match capture interrupt 0 Timer 0 Match Capture Interrupt Pend...

Page 103: ...d falling edges counter running OVF can occur 3 Timer 1 Counter Clear Bit 0 No effect when write 1 Clear T1 counter T1CNT when write 2 Timer 1 Overflow Interrupt Enable Bit note 0 Disable T1 overflow interrupt 1 Enable T1 overflow interrupt 1 Timer 1 Match Capture Interrupt Enable Bit 0 Disable T1 match capture interrupt 1 Enable T1 match capture interrupt 0 Timer 1 Match Capture Interrupt Pending...

Page 104: ...d falling edges counter running OVF can occur 3 Timer 2 Counter Clear Bit 0 No effect when write 1 Clear T2 counter T2CNT when write 2 Timer 2 Overflow Interrupt Enable Bit note 0 Disable T2 overflow interrupt 1 Enable T2 overflow interrupt 1 Timer 2 Match Capture Interrupt Enable Bit 0 Disable T2 match capture interrupt 1 Enable T2 match capture interrupt 0 Timer 2 Match Capture Interrupt Pending...

Page 105: ...he levels They are simply identifiers for the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup logic controlled by IPR register settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one...

Page 106: ...xpandable Figure 5 1 S3C8 S3F8 Series Interrupt Types The S3F80P5 microcontroller supports seventeen interrupt sources Thirteen of the interrupt sources have a corresponding interrupt vector address the remaining four interrupt sources share by one vector address Seven interrupt levels are recognized by the CPU in this device specific interrupt structure as shown in Figure 5 2 When multiple interr...

Page 107: ...2 0 external interrupt E6H P0 3 external interrupt IRQ6 E4H P0 2 external interrupt 3 E2H E0H 2 1 0 P0 1 external interrupt P0 0 external interrupt S W S W S W S W S W IRQ7 E8H P0 7 external interrupt P0 6 external interrupt P0 5 external interrupt P0 4 external interrupt S W S W S W S W F0H IRQ3 F2H Timer 2 match capture Timer 2 overflow S W H W 1 0 Figure 5 2 S3F80P5 Interrupt Structure NOTE Res...

Page 108: ...dresses The program reset address in the ROM is 0100H Reset address can be changed by smart option Refer to Table 13 3 or Figure 2 2 Internal Program Memory Flash 1 Kbyte Internal RAM Interrupt Vector Area ISP Sector Smart Option Rom Cell 65 536 Decimal 255 0 00H 0FFH FC00H FFFFH HEX 01FFH 02FFH 04FFH or 08FFH 03CH 03FH S3F80P5 18Kbyte Note 1 47FFH 16 383 Figure 5 3 ROM Vector Address Area NOTE Th...

Page 109: ...nal interrupt 232 E8H P0 5 external interrupt 232 E8H P0 4 external interrupt 230 E6H P0 3 external interrupt IRQ6 3 228 E4H P0 2 external interrupt 2 226 E2H P0 1 external interrupt 1 224 E0H P0 0 external interrupt 0 208 D0H P2 0 external interrupt IRQ4 NOTES 1 Interrupt priorities are identified in inverse order 0 is highest priority 1 is the next highest and so on 2 If two or more interrupts w...

Page 110: ...register IPR controls the relative priorities of interrupt levels The interrupt request register IRQ contains interrupt pending flags for each interrupt level as opposed to each interrupt source The system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 2 Interrupt Contr...

Page 111: ...settings IMR register Interrupt level priority settings IPR register Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing the part of your application program that handles the interrupt processing be sure to include the necessary register file address register pointer information Interrupt Request Register Read only IRQ0 IRQ7 Interrupts Inter...

Page 112: ...ote T2DATAH T2DATAL E8H E6H E7H Bank1 P0 7 external interrupt P0 6 external interrupt P0 5 external interrupt P0 4 external interrupt IRQ7 P0CONH P0INT P0PND E8H F1H F2H Bank0 P0 3 external interrupt P0 2 external interrupt P0 1 external interrupt P0 0 external interrupt IRQ6 P0CONL P0INT P0PND E9H F1H F2H Bank0 P2 0 external interrupt IRQ4 P2CONL P2INT P2PND EDH E5H E6H Bank0 NOTES 1 Because the ...

Page 113: ...cluded in the initialization routine which follows a reset operation in order to enable interrupt processing Although you can manipulate SYM 0 directly to enable and disable interrupts during normal operation we recommend using the EI and DI instructions for this purpose System Mode Register SYM DEH Set 1 Bank 0 R W 7 4 3 2 1 0 MSB LSB Fast Interrupt Level Selection Bits 0 0 0 0 0 1 0 1 0 0 1 1 1 ...

Page 114: ...ed to 0 interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 1and Bank0 Bit values can be read and written by instructions using the register addressing mode NOTE Before IMR register is changed to any value all interrupts must be disable Using DI...

Page 115: ... by the interrupt logic Please note that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 Group A IRQ0 IRQ1 Group B IRQ2 IRQ3 IRQ4 Group C IRQ6 IRQ7 IPR Group A IRQ1 A2 IRQ0 A1 IRQ6 C1 IRQ7 IPR Group C C2 IRQ2 B1 IPR Group B IRQ4 IRQ3 B21 B2 B22 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IP...

Page 116: ...0 IRQ0 IRQ1 1 IRQ0 IRQ1 Subgroup B see note 0 IRQ3 IRQ4 1 IRQ3 IRQ4 Group C 0 IRQ6 IRQ7 1 IRQ7 IRQ6 Group B 0 IRQ2 IRQ3 IRQ4 1 IRQ2 IRQ3 IRQ4 Group Priority 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Undefined B C A A B C B A C C A B C B A A C B Undefined D7 D4 D1 Not used Figure 5 8 Interrupt Priority Register IPR 5 12 ...

Page 117: ...me using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it You can however st...

Page 118: ...s type of pending bit is not mapped and cannot therefore be read or written by application software In the S3F80P5 interrupt structure the timer 0 overflow interrupt IRQ0 the timer 1 overflow interrupt IRQ1 and the counter A interrupt IRQ2 belong to this category of interrupts whose pending condition is cleared automatically by hardware Pending Bits Cleared by the Service Routine The second type o...

Page 119: ...M 0 1 The interrupt level must be enabled IMR register unmask The interrupt level must have the highest priority if more than one level is currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register If all of the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The CPU then initiates an interrupt...

Page 120: ...alue to the stack PUSH IMR 2 Load the IMR register with a new mask value that enables only the higher priority interrupt 3 Execute an EI instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs 4 When the lower priority interrupt service routine ends restore the IMR to its original value by returning the previous mask value from the stack POP IMR 5 Exec...

Page 121: ... enable bit in the SYM register Fast Interrupt Service Routine When an interrupt occurs in the level selected for fast interrupt processing the following events occur 1 The contents of the instruction pointer and the PC are swapped 2 The FLAG register values are written to the FLAGS FLAGS prime register 3 The fast interrupt status bit in the FLAGS register is set 4 The interrupt is serviced 5 Assu...

Page 122: ...INTERRUPT STRUCTURE S3F80P5_UM_ REV1 00 NOTES 5 18 ...

Page 123: ...and shift operations Data Types The SAM8 CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit Register Addressing To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a working reg...

Page 124: ... Load external data memory and increment LDCI dst src Load program memory and increment LDEPD dst src Load external data memory with pre decrement LDCPD dst src Load program memory with pre decrement LDEPI dst src Load external data memory with pre increment LDCPI dst src Load program memory with pre increment LDW dst src Load word POP dst Pop from stack POPUD dst src Pop user stack decrementing P...

Page 125: ...arry ADD dst src Add CP dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR 6 3 ...

Page 126: ...rc Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BITR dst Bit reset...

Page 127: ...ght RRC dst Rotate right through carry SRA dst Shift right arithmetic SWAP dst Swap nibbles CPU Control Instructions CCF Complement carry flag DI Disable interrupts EI Enable interrupts IDLE Enter Idle mode NOP No operation RCF Reset carry flag SB0 Set bank 0 SB1 Set bank 1 SCF Set carry flag SRP src Set register pointers SRP0 src Set register pointer 0 SRP1 src Set register pointer 1 STOP Enter S...

Page 128: ...r reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then simultaneously tw...

Page 129: ...tions D Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and cannot be used as a test condition H Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit 3 or when a su...

Page 130: ... logic one Set or cleared according to operation Value is unaffected x Value is undefined Table 6 3 Instruction Set Symbols Symbol Description dst Destination operand src Source operand Indirect register address prefix PC Program counter IP Instruction pointer FLAGS Flags register D5H RP Register pointer Immediate operand or register address prefix H Hexadecimal number suffix D Decimal number suff...

Page 131: ...ven number only Ir Indirect working register only Rn n 0 15 IR Indirect register or indirect working register Rn or reg reg 0 255 n 0 15 Irr Indirect working register pair only RRp p 0 2 14 IRR Indirect register pair or indirect working register pair RRp or reg reg 0 254 even only where p 0 2 14 X Indexed addressing mode reg Rn reg 0 255 n 0 15 XS Indexed short offset addressing mode addr RRp addr...

Page 132: ... r1 Ir2 TCM R2 R1 TCM IR2 R1 TCM R1 IM BAND r0 Rb I 7 PUSH R2 PUSH IR2 TM r1 r2 TM r1 Ir2 TM R2 R1 TM IR2 R1 TM R1 IM BIT r1 b B 8 DECW RR1 DECW IR1 PUSHUD IR1 R2 PUSHUI IR1 R2 MULT R2 RR1 MULT IR2 RR1 MULT IM RR1 LD r1 x r2 B 9 RL R1 RL IR1 POPUD IR2 R1 POPUI IR2 R1 DIV R2 RR1 DIV IR2 RR1 DIV IM RR1 LD r2 x r1 L A INCW RR1 INCW IR1 CP r1 r2 CP r1 Ir2 CP R2 R1 CP IR2 R1 CP R1 IM LDC r1 Irr2 xL E B...

Page 133: ...LOWER NIBBLE HEX 8 9 A B C D E F U 0 LD r1 R2 LD r2 R1 DJNZ r1 RA JR cc RA LD r1 IM JP cc DA INC r1 NEXT P 1 ENTER P 2 EXIT E 3 WFI R 4 SB0 5 SB1 N 6 IDLE I 7 STOP B 8 DI B 9 EI L A RET E B IRET C RCF H D SCF E E CCF X F LD r1 R2 LD r2 R1 DJNZ r1 RA JR cc RA LD r1 IM JP cc DA INC r1 NOP 6 11 ...

Page 134: ...110 note NZ Not zero Z 0 1101 PL Plus S 0 0101 MI Minus S 1 0100 OV Overflow V 1 1100 NOV No overflow V 0 0110 note EQ Equal Z 1 1110 note NE Not equal Z 0 1001 GE Greater than or equal S XOR V 0 0001 LT Less than S XOR V 1 1010 GT Greater than Z OR S XOR V 0 0010 LE Less than or equal Z OR S XOR V 1 1111 note UGE Unsigned greater than or equal C 0 0111 note ULT Unsigned less than C 1 1011 UGT Uns...

Page 135: ...ng The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Specific flag settings affected by the instruction Detailed description of the instruction s format execution time and addressin...

Page 136: ...f both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if there is a carry from the most significant bit of the low order four bits of the result cleared otherwise Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 12 r r 6 13 r lr opc src dst 3 6 14 R R 6 15 R IR opc dst src 3 6 16 R IM Examples Given R1 10H R2 03H C...

Page 137: ...e sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if a carry from the low order nibble occurred Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 02 r r 6 03 r lr opc src dst 3 6 04 R R 6 05 R IR opc dst src 3 6 06 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH ADD R1 R2 R1 15H R2 03H ADD R1 R2 R1 1CH R2...

Page 138: ...ise V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 52 r r 6 53 r lr opc src dst 3 6 54 R R 6 55 R IR opc dst src 3 6 56 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH AND R1 R2 R1 02H R2 03H AND R1 R2 R1 02H R2 03H AND 01H 02H Register 01H 01H register 02H 03H AND 01H 02H Register 01H 00H regist...

Page 139: ...rmat Bytes Cycles Opcode Hex Addr Mode dst src opc dst b 0 src 3 6 67 r0 Rb opc src b 1 dst 3 6 67 Rb r0 NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R1 07H and register 01H 05H BAND R1 01H 1 R1 06H register 01H 05H BAND 01H 1 R1 Register 01H 05H...

Page 140: ...ycles Opcode Hex Addr Mode dst src opc dst b 0 src 3 6 17 r0 Rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H and register 01H 01H BCP R1 01H 1 R1 07H register 01H 01H If destination working register R1 contains the value 07H 00000111B and the source register...

Page 141: ... Bytes Cycles Opcode Hex Addr Mode dst opc dst b 0 2 4 57 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITC R1 1 R1 05H If working register R1 contains the value 07H 00000111B the statement BITC R1 1 complements bit one of the destination and leaves the v...

Page 142: ...Format Bytes Cycles Opcode Hex Addr Mode dst opc dst b 0 2 4 77 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITR R1 1 R1 05H If the value of working register R1 is 07H 00000111B the statement BITR R1 1 clears bit one of the destination register R1 leavin...

Page 143: ... Bytes Cycles Opcode Hex Addr Mode dst opc dst b 1 2 4 77 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITS R1 3 R1 0FH If working register R1 contains the value 07H 00000111B the statement BITS R1 3 sets bit three of the destination register R1 to 1 leav...

Page 144: ...the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit Examples Given R1 07H and register 01H 03H BOR R1 01H 1 R1 07H register 01H 03H BOR 01H 2 R1 Register 01H 07H R1 07H In the first example destination working register R1 contains the value 07H 00000111B and source register 01H the value 03H 00000011B Th...

Page 145: ...ed Format Note 1 Bytes Cycles Opcode Hex Addr Mode dst src opc src b 0 dst 3 10 37 RA rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BTJRF SKIP R1 3 PC jumps to SKIP location If working register R1 contains the value 07H 00000111B the statement BTJRF SKIP R1 3 t...

Page 146: ... Format Note Bytes Cycles Opcode Hex Addr Mode dst src opc src b 1 dst 3 10 37 RA rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BTJRT SKIP R1 1 If working register R1 contains the value 07H 00000111B the statement BTJRT SKIP R1 1 tests bit one in the source reg...

Page 147: ... src opc dst b 0 src 3 6 27 r0 Rb opc src b 1 dst 3 6 27 Rb r0 NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R1 07H 00000111B and register 01H 03H 00000011B BXOR R1 01H 1 R1 06H register 01H 03H BXOR 01H 2 R1 Register 01H 07H R1 07H In the first e...

Page 148: ...instruction CALL RR0 SP 0000H 0000H 1AH 0001H 49H CALL 40H SP 0000H 0000H 1AH 0001H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to memory location 0000H The PC is then loaded with the value 3521H the address of the first instr...

Page 149: ...flag is changed to logic zero if C 0 the value of the carry flag is changed to logic one Flags C Complemented No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 EF Example Given The carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register 0D5H changing its value from logic zero to logic one 6 27 ...

Page 150: ... dst 2 4 B0 R 4 B1 IR Examples Given Register 00H 4FH register 01H 02H and register 02H 5EH CLR 00H Register 00H 00H CLR 01H Register 01H 02H register 02H 00H In Register R addressing mode the statement CLR 00H clears the destination register 00H value to 00H In the second example the statement CLR 01H uses Indirect Register IR addressing mode to clear the 02H register value to 00H 6 28 ...

Page 151: ...Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 60 R 4 61 IR Examples Given R1 07H and register 07H 0F1H COM R1 R1 0F8H COM R1 R1 07H register 07H 0EH In the first example destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and vice versa leaving the value 0F8H 11111000B In the secon...

Page 152: ...src dst 3 6 A4 R R 6 A5 R IR opc dst src 3 6 A6 R IM Examples 1 Given R1 02H and R2 03H CP R1 R2 Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value 03H The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative C and S are 1 2 Given R...

Page 153: ...ormat Bytes Cycles Opcode Hex Addr Mode dst src opc src dst RA 3 12 C2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Example Given R1 02H R2 03H and register 03H 02H CPIJE R1 R2 SKIP R2 04H PC jumps to SKIP location In this example working register R1 contains the value 02H working register R2 the value 03H and register 03 contains 02H The statement CPI...

Page 154: ...s Opcode Hex Addr Mode dst src opc src dst RA 3 12 D2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Example Given R1 02H R2 03H and register 03H 04H CPIJNER1 R2 SKIP R2 04H PC jumps to SKIP location Working register R1 contains the value 02H working register R2 the source pointer the value 03H and general register 03 the value 04H The statement CPIJNE R...

Page 155: ...ore DA Bits 4 7 Value Hex H Flag Before DA Bits 0 3 Value Hex Number Added to Byte Carry After DA 0 0 9 0 0 9 00 0 0 0 8 0 A F 06 0 0 0 9 1 0 3 06 0 ADD 0 A F 0 0 9 60 1 ADC 0 9 F 0 A F 66 1 0 A F 1 0 3 66 1 1 0 2 0 0 9 60 1 1 0 2 0 A F 66 1 1 0 3 1 0 3 66 1 0 0 9 0 0 9 00 00 0 SUB 0 0 8 1 6 F FA 06 0 SBC 1 7 F 0 0 9 A0 60 1 1 6 F 1 6 F 9A 66 1 Flags C Set if there was a carry from the most signif...

Page 156: ... 27 the result should be 42 The sum is incorrect however when the binary representations are added in the destination location using standard binary arithmetic 0 0 0 1 0 1 0 1 15 0 0 1 0 0 1 1 1 27 0 0 1 1 1 1 0 0 3CH The DA instruction adjusts this result so that the correct BCD representation is obtained 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 42 Assuming the same values given above the ...

Page 157: ...cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 00 R 4 01 IR Examples Given R1 03H and register 03H 10H DEC R1 R1 02H DEC R1 Register 03H 0FH In the first example if working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC R1 decrements t...

Page 158: ...s Opcode Hex Addr Mode dst opc dst 2 8 80 RR 8 81 IR Examples Given R0 12H R1 34H R2 30H register 30H 0FH and register 31H 21H DECW RR0 R0 12H R1 33H DECW R2 Register 30H 0FH register 31H 20H In the first example destination register R0 contains the value 12H and register R1 the value 34H The statement DECW RR0 addresses R0 and the following operand R1 as a 16 bit word and decrements the value of ...

Page 159: ...tive interrupt pending bits but the CPU will not service them while interrupt processing is disabled Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 8F Example Given SYM 01H DI If the value of the SYM register is 01H the statement DI leaves the new value 00H in the register and clears SYM 0 to 0 disabling interrupt processing Before changing IMR interrupt pending and interrupt s...

Page 160: ...ient 1 cleared otherwise V Set if quotient is 28 or if divisor 0 cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM NOTE Execution takes 10 cycles if the divide by zero is attempted otherwise it takes 26 cycles Examples Given R0 10H R1 03H R2 40H register 40H 80H DIVRR0 R2 R0 03H R1 40H DIVRR0 R2 R0...

Page 161: ...ing used as a counter should be set at the one of location 0C0H to 0CFH with SRP SRP0 or SRP1 instruction Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst r opc dst 2 8 jump taken rA RA 8 no jump r 0 to F Example Given R1 02H and LOOP is the label of a relative address SRP 0C0H DJNZ R1 LOOP DJNZ is typically used to control a loop of instructions In many cases a label is us...

Page 162: ...ending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when you execute the EI instruction Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 9F Example Given SYM 00H EI If the SYM register contains the value 00H that is if interrupts are currently disabled the statement EI sets the SYM register to 01H enabling all interrupts SY...

Page 163: ... the instruction pointer is loaded into the PC and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 1F Example The diagram below shows one example of how to use an ENTER statement 0050 IP 0022 SP 22 Data Address Data 0040 PC 40 41 42 43 Enter Address H Address L Address H Address Data 1F 01 10 Memory 0043 IP 0020 SP 20 21 22 IPH IPL ...

Page 164: ... is then loaded into the program counter and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 internal stack 2F 16 internal stack Example The diagram below shows one example of how to use an EXIT statement 0050 IP 0022 SP Address Data 0040 PC Address Data Memory 0052 IP 0022 SP Address Data 0060 PC Address Data Memory Stack Stack Bef...

Page 165: ...lock while allowing system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc 1 4 6F Example The instruction IDLE stops the CPU clock but not the system clock 6 43 ...

Page 166: ...de dst dst opc 1 4 rE r r 0 to F opc dst 2 4 20 R 4 21 IR Examples Given R0 1BH register 00H 0CH and register 1BH 0FH INCR0 R0 1CH INC00H Register 00H 0DH INC R0 R0 1BH register 01H 10H In the first example if destination working register R0 contains the value 1BH the statement INC R0 leaves the value 1CH in that same register The next example shows the effect an INC instruction has on register 00...

Page 167: ...gister 02H 0FH and register 03H 0FFH INCW RR0 R0 1AH R1 03H INCW R1 Register 02H 10H register 03H 00H In the first example the working register pair RR0 contains the value 1AH in register R0 and 02H in register R1 The statement INCW RR0 increments the 16 bit destination by one leaving the value 03H in register R1 In the second example the statement INCW R1 uses Indirect Register IR addressing mode...

Page 168: ...Fast Bytes Cycles Opcode Hex opc 1 6 BF Example In the figure below the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled When an interrupt occurs the program counter and instruction pointer are swapped This causes the PC to jump to address 100H and the IP to keep the return address The last instruction in the service routine normally is a jump to ...

Page 169: ... byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 In the first byte of the three byte instruction format conditional jump the condition code and the opcode are both four bits Examples Given The carry flag C 1 register 00 01H and register 01 20H JP C LABEL_W LABEL_W 1000H PC 1000H JP 00H PC 0120H The first example shows a conditional JP Assuming that the ...

Page 170: ...original value of the program counter is taken to be the address of the first instruction byte following the JR statement Flags No flags are affected Format 1 Bytes Cycles Opcode Hex Addr Mode dst cc opc dst 2 6 ccB RA cc 0 to F NOTE In the first byte of the two byte instruction format the condition code and the opcode are each four bits Example Given The carry flag 1 and LABEL_X 1FF7H JR C LABEL_...

Page 171: ...ntents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src dst opc src 2 4 rC r IM 4 r8 r R src opc dst 2 4 r9 R r r 0 to F opc dst src 2 4 C7 r lr 4 D7 Ir r opc src dst 3 6 E4 R R 6 E5 R IR opc dst src 3 6 E6 R IM 6 D6 IR IM opc src dst 3 6 F5 IR R opc dst src x 3 6 87 r x r opc src dst x 3 6 97 x r r 6 49 ...

Page 172: ...er 01H 20H LD 01H R0 Register 01H 01H R0 01H LD R1 R0 R1 20H R0 01H LD R0 R1 R0 01H R1 0AH register 01H 0AH LD 00H 01H Register 00H 20H register 01H 20H LD 02H 00H Register 02H 20H register 00H 01H LD 00H 0AH Register 00H 0AH LD 00H 10H Register 00H 01H register 01H 10H LD 00H 02H Register 00H 01H register 01H 02 register 02H 02H LD R0 LOOP R1 R0 0FFH R1 0AH LD LOOP R0 R1 Register 31H 0AH R0 01H R...

Page 173: ...s the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R0 06H and general register 00H 05H LDB R0 00H 2 R0 07H register 00H 05H LDB 00H 0 R0 R0 06H register 00H 04H In the first example destination working register R0 contains the value 06H and the source general register 00H the value 05H The statement LD R0 0...

Page 174: ... E7 r XS rr 4 opc src dst XS 3 12 F7 XS rr r 5 opc dst src XLL XLH 4 14 A7 r XL rr 6 opc src dst XLL XLH 4 14 B7 XL rr r 7 opc dst 0000 DAL DAH 4 14 A7 r DA 8 opc src 0000 DAL DAH 4 14 B7 DA r 9 opc dst 0001 DAL DAH 4 14 A7 r DA 10 opc src 0001 DAL DAH 4 14 B7 DA r NOTES 1 The source src or working register pair rr for formats 5 and 6 cannot use register pair 0 1 2 For formats 3 and 4 the destinat...

Page 175: ...tion 0105H 01H RR2 R0 6DH R2 01H R3 04H LDE R0 01H RR2 R0 contents of external data memory location 0105H 01H RR2 R0 7DH R2 01H R3 04H LDC note 01H RR2 R0 11H contents of R0 is loaded into program memory location 0105H 01H 0104H LDE 01H RR2 R0 11H contents of R0 is loaded into external data memory location 0105H 01H 0104H LDC R0 1000H RR2 R0 contents of program memory location 1104H 1000H 0104H R0...

Page 176: ...ted LDCD references program memory and LDED references external data memory The assembler makes Irr an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 10 E2 r Irr Examples Given R6 10H R7 33H R8 12H program memory location 1033H 0CDH and external data memory location 1033H 0DDH LDCD R8 RR6 0...

Page 177: ...ffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes Irr even for program memory and odd for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 10 E3 r Irr Examples Given R6 10H R7 33H R8 12H program memory locations 1033H 0CDH and 1034H 0C5H external data memory locations 1033H 0DDH and 1034H 0D5H LDC...

Page 178: ...ation The contents of the source are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes Irr an even number for program memory and an odd number for external data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 2 14 F2 Irr r Examples Given R0 77H R6 30H and R7 00H LDCPD RR6 R0 RR6 RR6 1 77H contents ...

Page 179: ...ocation The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 2 14 F3 Irr r Examples Given R0 7FH R6 21H and R7 0FFH LDCPI RR6 R0 RR6 RR6 1 7FH contents of R0 ...

Page 180: ...H and register 03H 0FH LDW RR6 RR4 R6 06H R7 1CH R4 06H R5 1CH LDW 00H 02H Register 00H 03H register 01H 0FH register 02H 03H register 03H 0FH LDW RR2 R7 R2 03H R3 0FH LDW 04H 01H Register 04H 03H register 05H 0FH LDW RR6 1234H R6 12H R7 34H LDW 02H 0FEDH Register 02H 0FH register 03H 0EDH In the second example please note that the statement LDW 00H 02H loads the contents of the source word 02H 03...

Page 181: ...result is a 1 cleared otherwise V Cleared D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 22 84 RR R 22 85 RR IR 22 86 RR IM Examples Given Register 00H 20H register 01H 03H register 02H 09H register 03H 06H MULT 00H 02H Register 00H 01H register 01H 20H register 02H 09H MULT 00H 01H Register 00H 00H register 01H 0C0H MULT 00H 30H Register 00H 06H register ...

Page 182: ...ram counter The instruction pointer is then incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 10 0F Example The following diagram shows one example of how to use the NEXT instruction Data 01 10 Before After 0045 IP Address Data 0130 PC 43 44 45 Address H Address L Address H Address Data Memory 130 Routine 0043 IP Address Data 0120 PC 43 44 45 Address H Address L A...

Page 183: ...uction Typically one or more NOPs are executed in sequence in order to effect a timing delay of variable duration Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 FF Example When the instruction NOP is encountered in a program no operation occurs Instead there is a delay in instruction execution time 6 61 ...

Page 184: ...ormat Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 42 r r 6 43 r lr opc src dst 3 6 44 R R 6 45 R IR opc dst src 3 6 46 R IM Examples Given R0 15H R1 2AH R2 01H register 00H 08H register 01H 37H and register 08H 8AH OR R0 R1 R0 3FH R1 2AH OR R0 R2 R0 37H R2 01H register 01H 37H OR 00H 01H Register 00H 3FH register 01H 37H OR 01H 00H Register 00H 08H register 01H 0BFH OR 00H 02H Regist...

Page 185: ...pc dst 2 8 50 R 8 51 IR Examples Given Register 00H 01H register 01H 1BH SPH 0D8H 00H SPL 0D9H 0FBH and stack register 0FBH 55H POP 00H Register 00H 55H SP 00FCH POP 00H Register 00H 01H register 01H 55H SP 00FCH In the first example general register 00H contains the value 01H The statement POP 00H loads the contents of location 00FBH 55H into destination register 00H and then increments the stack...

Page 186: ...ecremented Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 8 92 R IR Example Given Register 00H 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02H 00H Register 00H 41H register 02H 6FH register 42H 6FH If general register 00H contains the value 42H and register 42H the value 6FH the statement POPUD 02H 00H loads the contents o...

Page 187: ...inter is then incremented Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc src dst 3 8 93 R IR Example Given Register 00H 01H and register 01H 70H POPUI 02H 00H Register 00H 02H register 01H 70H register 02H 70H If general register 00H contains the value 01H and register 01H the value 70H the statement POPUI 02H 00H loads the value 70H into the destination general r...

Page 188: ...nternal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Examples Given Register 40H 4FH register 4FH 0AAH SPH 00H and SPL 00H PUSH 40H Register 40H 4FH stack register 0FFH 4FH SPH 0FFH SPL 0FFH PUSH 40H Register 40H 4FH register 4FH 0AAH stack register 0FFH 0AAH SPH 0FFH SPL 0FFH In the first example if the stack pointer contains the value 0000H and general register 40H the val...

Page 189: ...pointer Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 3 8 82 IR R Example Given Register 00H 03H register 01H 05H and register 02H 1AH PUSHUD 00H 01H Register 00H 02H register 01H 05H register 02H 05H If the user stack pointer register 00H for example contains the value 03H the statement PUSHUD 00H 01H decrements the user stack pointer by one leaving the ...

Page 190: ...stack pointer Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 3 8 83 IR R Example Given Register 00H 03H register 01H 05H and register 04H 2AH PUSHUI 00H 01H Register 00H 04H register 01H 05H register 04H 05H If the user stack pointer register 00H for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer by one leavin...

Page 191: ...F Operation C 0 The carry flag is cleared to logic zero regardless of its previous value Flags C Cleared to 0 No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 CF Example Given C 1 or 0 The instruction RCF clears the carry flag C to logic zero 6 69 ...

Page 192: ...ecuted is the one that is addressed by the new program counter value Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 8 internal stack AF 10 internal stack Example Given SP 00FCH SP 101AH and PC 1234 RET PC 101AH SP 00FEH The statement RET pops the contents of stack pointer location 00FCH 10H into the high byte of the program counter The stack pointer then pops the value in locatio...

Page 193: ...0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 90 R 4 91 IR Examples Given Register 00H 0AAH register 01H 02H and register 02H 17H RL 00H Register 00H 55H C 1 RL 01H Register 01H 02H register 02H 2EH C 0 In the first example if general r...

Page 194: ...etic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 10 R 4 11 IR Examples Given Register 00H 0AAH register 01H 02H and register 02H 17H C 0 RLC 00H Register 00H 54H C 1 RLC 01H Register 01H 02H register 02H 2EH C 0 In the first example if general register 00H has t...

Page 195: ...curred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 E0 R 4 E1 IR Examples Given Register 00H 31H register 01H 02H and register 02H 17H RR 00H Register 00H 98H C 1 RR 01H Register 01H 02H register 02H 8BH C 1 In the first example if general register 00H contains the value 31H 00110...

Page 196: ...tic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 C0 R 4 C1 IR Examples Given Register 00H 55H register 01H 02H register 02H 17H and C 0 RRC 00H Register 00H 2AH C 1 RRC 01H Register 01H 02H register 02H 0BH C 1 In the first example if general register 00H contain...

Page 197: ...s the bank address flag in the FLAGS register FLAGS 0 to logic zero selecting bank 0 register addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 4F Example The statement SB0 clears FLAGS 0 to 0 selecting bank 0 register addressing 6 75 ...

Page 198: ...egister FLAGS 0 to logic one selecting bank 1 register addressing in the set 1 area of the register file Bank 1 is not implemented in some S3F8 series microcontrollers Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 5F Example The statement SB1 sets FLAGS 0 to 1 selecting bank 1 register addressing if implemented 6 76 ...

Page 199: ...at is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 32 r r 6 33 r lr opc src dst 3 6 34 R R 6 35 R IR opc d...

Page 200: ...rry Flag SCF Operation C 1 The carry flag C is set to logic one regardless of its previous value Flags C Set to 1 No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 DF Example The statement SCF sets the carry flag to logic one 6 78 ...

Page 201: ...et if the result is negative cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 D0 R 4 D1 IR Examples Given Register 00H 9AH register 02H 03H register 03H 0BCH and C 1 SRA 00H Register 00H 0CD C 0 SRA 02H Register 02H 03H register 03H 0DEH C 0 In the first example if general register 00H contains the value 9AH 10011010B the st...

Page 202: ... write one or both of the register pointers RP0 and RP1 Bits 3 7 of the selected register pointer are written unless both register pointers are selected RP0 3 is then cleared to logic zero and RP1 3 is set to logic one Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode src opc src 2 4 31 IM Examples The statement SRP 40H sets register pointer 0 RP0 at location 0D6H to 40H and reg...

Page 203: ... peripheral registers and I O port control and data registers are retained Stop mode can be released by an external reset operation or by external interrupts For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed Flags No flags are affected Format Bytes Cycles Opcode Hex Addr Mode dst src opc 1 4 7F Example The statement ST...

Page 204: ...rwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 22 r r 6 23 r lr opc src dst 3 6 24 R R 6 25 R IR opc dst src 3 6 26 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH SUB R1 R2 R1 0FH R2 03...

Page 205: ...7 is set cleared otherwise V Undefined D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst opc dst 2 4 F0 R 4 F1 IR Examples Given Register 00H 3EH register 02H 03H and register 03H 0A4H SWAP 00H Register 00H 0E3H SWAP 02H Register 02H 03H register 03H 4AH In the first example if general register 00H contains the value 3EH 00111110B the statement SWAP 00H swaps the lower and upp...

Page 206: ...red to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 62 r r 6 63 r lr opc src dst 3 6 64 R R 6 65 R IR opc dst src 3 6 66 R IM Examples Given R0 0C7H R1 02H R2 12H register 00H 2BH register 01H 02H and register 02H 23H TCM R0 R1 R0 0C7H R1 02H Z 1 TCM R0 R1 R0 0C7H R1 02H register 02H 23H Z 0 TCM 00H 01H Register 00H 2BH register 01H 02H Z 1 TCM 00H 0...

Page 207: ... Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 72 r r 6 73 r lr opc src dst 3 6 74 R R 6 75 R IR opc dst src 3 6 76 R IM Examples Given R0 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H TM R0 R1 R0 0C7H R1 02H Z 0 TM R0 R1 R0 0C7H R1 02H register 02H 23H Z 0 TM 00H 01H Register 00H 2BH register 01H 02H Z 0 TM 00H 01H Register 00H 2BH register 01H 02H r...

Page 208: ...leased by an internal interrupt including a fast interrupt Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4n 3F n 1 2 3 Example The following sample program structure shows the sequence of operations that follow a WFI statement EI WFI Next instruction Main program Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed Enable global interrup...

Page 209: ...ffected H Unaffected Format Bytes Cycles Opcode Hex Addr Mode dst src opc dst src 2 4 B2 r r 6 B3 r lr opc src dst 3 6 B4 R R 6 B5 R IR opc dst src 3 6 B6 R IM Examples Given R0 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H XOR R0 R1 R0 0C5H R1 02H XOR R0 R1 R0 0E4H R1 02H register 02H 23H XOR 00H 01H Register 00H 29H register 01H 02H XOR 00H 01H Register 00H 08H regist...

Page 210: ...INSTRUCTION SET S3F80P5_UM_ REV1 00 NOTES 6 88 ...

Page 211: ...e external oscillator or clock source to the on chip clock circuit Typically application systems have a resister and two separate capacitors across the power pins in order to suppress high frequency noise and provide bulk charge storage for the overall system SYSTEM CLOCK CIRCUIT The system clock circuit has the following components External crystal or ceramic resonator oscillation source or an ex...

Page 212: ...LOCK AND POWER CIRCUITS S3F80P5_UM_ REV1 00 XIN XOUT C1 C2 Figure 7 1 Main Oscillator Circuit External Crystal or Ceramic Resonator XIN XOUT External Clock Open Pin Figure 7 2 External Clock Circuit 7 2 ...

Page 213: ... register is automatically cleared In Idle mode the internal clock signal is gated away from the CPU but continues to be supplied to the interrupt structure timer 0 timer 1 counter A and so on Idle mode is released by a reset or by an interrupt external or internally generated NOTES 1 An external interrupt with an RC delay noise filter for the S3F80P5 INT0 5 is fixed to release stop mode and wake ...

Page 214: ... 0 Bit are not used in S3F80P5 After a reset the main oscillator is activated and the fOSC 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed to fOSC fOSC 2 fOSC 8 or fOSC 16 System Clock Control Register CLKCON D4H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB Not used Divide by selection bits for CPU clock frequency 00 fosc 16 01 fosc 8 10 f...

Page 215: ...storage for the overall system We recommend that R1 10ohm C1 0 1uF and C2 100uF VDD VBAT 3 6V Note 2 VBAT 1 55V VF VR Note1 VF VDD falling time should be at least 100us for stabilized IVC VDD VR VDD rising time should be at least 500us for stabilized IVC VDD Figure 7 6 Guide Line of Chip Operating Voltage Table 7 1 Falling and Rising Time of Operating Voltage VDD Slope Min Typ Max Unit VF 100 VR 5...

Page 216: ...CLOCK AND POWER CIRCUITS S3F80P5_UM_ REV1 00 NOTES 7 6 ...

Page 217: ...set is generated whenever the basic timer overflow occurs Low Voltage Detect LVD When VDD is changed in condition for LVD operation in the normal operating mode reset occurs Internal Power ON Reset IPOR When VDD is changed in condition for IPOR operation a reset is generated External Interrupt INT0 INT5 When RESET Control Bit is set to 0 smart option 03FH and chip is in stop mode if external inter...

Page 218: ...en POR circuit detects VDD below V reset is generated by internal power on reset POR 3 Basic Timer over flow for watchdog timer See the chapter 10 Basic Timer and Timer 0 for more understanding 4 When RESET Control Bit smart option 03FH is set to 0 and chip is in stop mode external interrupt input by P0 and P2 0 generates the reset signal 5 When RESET Control Bit smart option 03FH are set to 0 and...

Page 219: ...INT0 INT5 SED R Circuit P0 STOP STOPCON Back up Mode Falling Edge Detector Enable Disable STOP STOPCON LVD IPOR Rising Edge Detector fosc BT WDT Falling Edge RESET RESET Contorl Bit 1 RESET Contorl Bit 1 STOP STOPCON RESET Control Bit smart option bit 0 03FH Figure 8 2 RESET Block Diagram of the S3F80P5 8 3 ...

Page 220: ...Timer Counter BTCNT isn t cleared within a specific time by program For more understanding of the watchdog timer function please see the chapter 10 Basic Timer and Timer0 LVD RESET The Low Voltage Detect Circuit LVD is built on the S3F80P5 product to generate a system reset LVD is disabled in stop mode When the voltage at VDD is falling down and passing VLVD the chip goes into back up mode at the ...

Page 221: ...oduct When power is initially applied to the MCU or when VDD drops below the VPOR the POR circuit holds the MCU in reset until VDD has risen above the VLVD level Normal Operating Mode VDD VLVD tWAIT VPOR Internal RESET Release Reset Pulse Figure 8 4 Timing Diagram for Internal Power On Reset Circuit 8 5 ...

Page 222: ...ion starts Reset Low If Vreset VIH the operating status is in STOP mode LVD circuit is disabled in the S3F80P5X Figure 8 5 Reset Timing Diagram for the S3F80P5 in STOP Mode by IPOR EXTERNAL INTERRUPT RESET When RESET Control Bit smart option 03FH is set to 0 and chip is in stop mode if external interrupt is occurred by among the enabled external interrupt sources from INT0 to INT5 reset signal is ...

Page 223: ...normal state the falling edge input of P0 generates the reset signal Refer to following table and figure for more information Table 8 1 Reset Condition in STOP Mode Condition Slope of VDD VDD Reset Source System Reset Rising up from VPOR VDD VLVD VDD VLVD No system reset Rising up from VDD VPOR VDD VLVD Internal POR System reset occurs 8 7 ...

Page 224: ...rol registers are reset to their default values and the contents of all data registers are retained The reset automatically selects the slowest clock 1 16 because of the hardware reset value for the CLKCON register If all interrupts are masked in the IMR register a reset is the only way you can release Idle mode 2 Activate any enabled interrupt internal or external When you use an interrupt to rel...

Page 225: ...rk of LVD circuit The system reset of watchdog timer is not occurred in back up mode LVD Rising Edge Detector Back Up Mode Falling Edge Detector VDD VLVD Figure 8 6 Block Diagram for Back up Mode Normal Operation Normal Operation Back up Mode Voltage V VLVD VDD Low level detect voltage Falling edge detected oscillation stop VDD V LVD Rising edge detected VDD V LVD Reset Pulse generated oscillation...

Page 226: ...e VDD VLVD tWAIT VPOR Stop Mode LVD off Key in Normal Operating Mode VDD VLVD tWAIT VPOR Stop Mode LVD off Key in Back up Mode Reset pulse generated oscillation start LVD ON LVD ON Figure 8 8 Timing Diagram for Back up Mode Input in Stop Mode 8 10 ...

Page 227: ...al register file is retained STOP mode can be released in one of two ways by a system reset or by an external interrupt After releasing from STOP mode the value of stop control register STOPCON is cleared automatically PROGRAMMING TIP To Enter STOP Mode This example shows how to enter the stop mode ORG 0000H Reset address JP T START ENTER_STOP LD STOPCON 0A5H STOP NOP NOP NOP RET ORG 0100H 3 JP T ...

Page 228: ... 03FH and external interrupt is enabled S3F80P5 is released from stop mode and generates reset signal On the other hand when RESET Control Bit are set to 1 smart option 03FH S3F80P5 is only released from stop mode and does not generate reset signal To wake up from stop mode by external interrupt from INT0 to INT5 external interrupt should be enabled by setting corresponding control registers or in...

Page 229: ...enerates reset signal On the other hand when RESET Control Bit is set to 1 smart option 03FH S3F80P5 is only released stop mode reset doesn t occur When the falling edge of a pin on Port0 is entered the chip is released from stop mode even though external interrupt is disabled Keeping the chip from entering abnormal stop mode This circuit detects the abnormal status by checking the port P0 status ...

Page 230: ...s are disabled The watch dog function Basic Timer is enabled Port 0 2 and 3 are set to input mode and all pull up resistors are disabled for the I O port pin circuits Peripheral control and data register settings are disabled and reset to their default hardware values See Table 8 2 The program counter PC is loaded with the program reset address in the ROM 0100H When the programmed oscillation stab...

Page 231: ... 0 0 0 0 0 0 0 System Flags Register FLAGS 213 D5H x x x x x x 0 0 Register Pointer 0 RP0 214 D6H 1 1 0 0 0 Register Pointer 1 RP1 215 D7H 1 1 0 0 1 Location D8H SPH is not mapped Stack Pointer Low Byte SPL 217 D9H x x x x x x x x Instruction Pointer High Byte IPH 218 DAH x x x x x x x x Instruction Pointer Low Byte IPL 219 DBH x x x x x x x x Interrupt Request Register Read Only IRQ 220 DCH 0 0 0...

Page 232: ... 1 1 1 1 1 1 1 1 Timer 1 Counter Register High Byte T1CNTH 246 F6H 0 0 0 0 0 0 0 0 Timer 1 Counter Register Low Byte T1CNTL 247 F7H 0 0 0 0 0 0 0 0 Timer 1 Data Register High Byte T1DATAH 248 F8H 1 1 1 1 1 1 1 1 Timer 1 Data Register Low Byte T1DATAL 249 F9H 1 1 1 1 1 1 1 1 Timer 1 Control Register T1CON 250 FAH 0 0 0 0 0 0 0 0 STOP Control Register STOPCON 251 FBH 0 0 0 0 0 0 0 0 Locations FCH is...

Page 233: ...ter T2CON 232 E8H 0 0 0 0 0 0 0 0 Not mapped in address E9H to EB Flash Memory Sector Address Register High Byte FMSECH 236 ECH 0 0 0 0 0 0 0 0 Flash Memory Sector Address Register Low byte FMSECL 237 EDH 0 0 0 0 0 0 0 0 Flash Memory User Programming Enable Register FMUSR 238 EEH 0 0 0 0 0 0 0 0 Flash Memory Control Register FMCON 239 EFH 0 0 0 0 0 Reset Indicating Register RESETID 240 F0H Refer t...

Page 234: ... Continue O STOP Release and Reset Stop Mode SED R P2 0 X STOP X STOP NOTES 1 X means that a corresponding reset source don t generate reset signal O means that a corresponding reset source generates reset signal 2 Reset means that reset signal is generated and chip reset occurs 3 Continue means that it executes the next instruction continuously without ISR execution 4 External ISR means that chip...

Page 235: ...l up Resister No Connection for Pins P0CONH 00H or 0FFH P0CONL 00H or 0FFH P0PUR 0FFH Port 1 Set Open Drain Output mode Set P1 Data Register to 00H Disable Pull up Resister No Connection for Pins P1CONH 55H P1CONL 55H P1 00H Port 2 0 Set Push pull Output mode Set P2 Data Register to 00H Disable Pull up resister No Connection for Pins P2CONL 0AAH P2 00H P2PUR 00H P3 0 3 1 Set Push pull Output mode ...

Page 236: ...l the ports become input mode but is blocked Disable all pull up resister All I O port is floating status Disable all pull up resisters All the ports keep the previous status Output port data is not changed Control Register All control register and system register are initialized as list of Table 8 2 All control register and system register are initialized as list of Table 8 2 Releasing Condition ...

Page 237: ... pins Each port is bit programmable and can be flexibly configured to meet application design requirements The CPU accesses ports by directly writing or reading port registers No special I O instructions are required For IR applications port0 port1 are usually configured to the keyboard matrix port2 is normal I O pin and port 3 is used to IR drive pins Table 9 1 9 2 and 9 3 give you a general over...

Page 238: ...h pull up open drain output or push pull output This port is dedicated for key output in IR controller application Port 2 1 bit general purpose I O port Input push pull output or open drain output The P2 0 can be used as external interrupt inputs and have noise filters The P2INT register is used to enable disable interrupts and P2PND bits can be polled by software for interrupt pending control Pul...

Page 239: ...ata register P1 225 E1H Set 1 Bank 0 R W Port 2 data register P2 226 E2H Set 1 Bank 0 R W Port 3 data register P3 227 E3H Set 1 Bank 0 R W Because port 3 is a 2 bit I O port the port 3 data register only contains values for P3 0 P3 1 The P3 register also contains a special carrier on off bit P3 7 See the port3 description for details All other I O ports except P2 are 8 bit Pn 4 Pn 3 7 6 5 4 3 2 1 ...

Page 240: ...er addressing mode You can assign a pull up resistor to the port 3 pins P3 0 P3 1 in the input mode using basic port configuration setting in the P3CON registers Pn 4 Pn 3 Set 1 E7H Bank0 R W Pull up Register Enable Registers PnPUR where n 0 7 6 5 4 3 2 1 0 MSB LSB Pn 1 Pn 2 Pn 5 Pn 6 Pn 7 Pn 0 NOTE Pull up resistors can be assigned to the port 3 pins P3 0 P3 1 by making the appropriate setting th...

Page 241: ...8 bit basic timer counter BTCNT FDH Set 1 Bank0 Read only Basic timer control register BTCON D3H Set 1 Bank0 R W TIMER 0 Timer 0 has three operating modes one of which you select using the appropriate T0CON setting Interval timer mode Capture input mode with a rising or falling edge trigger at the P3 0 pin PWM mode Timer 0 has the following functional components Clock frequency divider fOSC divide...

Page 242: ...o disable the watch dog function you must write the signature code 1010B to the basic timer register control bits BTCON 7 BTCON 4 For improved reliability using the watch dog timer function is recommended in remote controllers and hand held product applications Basic Timer Control Register BTCON D3H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB Divider Clear Bit for BT and T0 0 No effect 1 Clear both d...

Page 243: ... BTCNT clear instruction If a malfunction does occur a reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when Stop mode has been released by an external interrupt In Stop mode whenever a reset or an external interrupt occurs the oscillator starts The BTCNT...

Page 244: ... input clock frequency of fOSC 4096 and disables all timer 0 interrupts You can clear the timer 0 counter at any time during normal operation by writing a 1 to T0CON 3 The timer 0 overflow interrupt T0OVF is interrupt level IRQ0 and has the vector address FAH When a timer0 overflow interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware To enable the ...

Page 245: ...ck Selection Bits 00 fOSC 4096 01 fOSC 256 10 fOSC 8 11 External clock NOTE Timer 0 Counter Clear Bit 0 No effect 1 Clear the timer 0 counter when write Timer 0 Operating Mode Selection Bits 00 Interval mode 01 Capture mode capture on rising edge counter running OVF can occur 10 Capture mode capture on falling edge counter running OVF can occur 11 PWM mode OVF interrupt can occur NOTE The external...

Page 246: ...erval Timer Mode In interval timer mode a match signal is generated when the counter value is identical to the value written to the T0 reference data register T0DATA The match signal generates a timer 0 match interrupt T0INT vector FCH and clears the counter If for example you write the value 10H to T0DATA 0BH to T0CON the counter will increment until it reaches 10H At this point the T0 interrupt ...

Page 247: ...t interrupts are not typically used in PWM type applications Instead the pulse at the T0PWM pin is held to low level as long as the reference data value is less than or equal to the counter value and then the pulse is held to high level for as long as the data value is greater than the counter value One pulse width is equal to tCLK 256 See Figure 10 5 Match CTL T0CON 5 T0CON 4 P3 0 T0PWM IRQ0 T0OV...

Page 248: ...o 0 normal I O port P3 0 is selected Both kinds of timer 0 interrupts can be used in capture mode the timer 0 overflow interrupt is generated whenever a counter overflow occurs the timer 0 match capture interrupt is generated whenever the counter value is loaded into the T0 data register By reading the captured data value in T0DATA and assuming a specific value for the timer 0 clock frequency you ...

Page 249: ...ite 1010xxxxB to disable Bits7 6 Bits3 2 Bit 1 RESETor STOP Timer0 Overflow Bit 2 Timer0 Match T0PWM Basic Timer Control Register Timer0 Control Register Match Signal T0CON 3 T0OVF Data Bus Timer0 Data Register T0DATA 1 4096 1 8 1 256 1 4096 1 1024 1 128 P3 0 T0CAP Bits5 4 R P3 1 T0CK GND Bit 3 1 16384 NOTES 1 During a power on reset operation the CPU is idle during the required oscillation stabil...

Page 250: ...T DI Disable all interrupts LD BTCON 0AAH Disable the watchdog timer LD CLKCON 18H Non divided clock CLR SYM Disable global and fast interrupts CLR SPL Stack pointer low byte 0 Stack area starts at 0FFH SRP 0C0H Set register pointer 0C0H EI Enable interrupts MAIN LD BTCON 52H Enable the watchdog timer Basic timer clock fOSC 4096 Clear basic timer counter NOP NOP JP T MAIN 10 10 ...

Page 251: ...w interrupt VECTOR 00FCH T0INT Timer 0 match capture interrupt ORG 0100H RESET DI Disable all interrupts LD BTCON 0AAH Disable the watchdog timer LD CLKCON 18H Select non divided clock CLR SYM Disable global and fast interrupts CLR SPL Stack pointer low byte 0 Stack area starts at 0FFH LD T0CON 4BH Write 00100101B Input clock is fOSC 256 Interval timer mode Enable the timer 0 interrupt Disable the...

Page 252: ...AMMING TIP Programming Timer 0 Continued CP R0 32H 50 4 200 ms JR ULT NO_200MS_SET BITS R1 2 Bit setting 61 2H NO_200MS_SET LD T0CON 42H Clear pending bit POP RP0 Restore register pointer 0 value T0OVER IRET Return from interrupt service routine 10 12 ...

Page 253: ...k Oscillator frequency fOSC divided by 4 8 or 16 Internal clock input from the counter A module counter A flip flop output You can use Timer 1 in three ways As a normal free run counter generating a Timer 1 overflow interrupt IRQ1 vector F4H at programmed time intervals To generate a Timer 1 match interrupt IRQ1 vector F6H when the 16 bit Timer 1 count value matches the 16 bit value written to the...

Page 254: ... interrupt IRQ1 vector F6H whenever a triggering condition is detected at the P3 0 pin The T1CON 5 and T1CON 4 bit pair setting is used to select the trigger condition for capture mode operation rising edges falling edges or both signal edges In capture mode program software can poll the Timer 1 match capture interrupt pending bit T1CON 0 to detect when a Timer 1 capture interrupt pending conditio...

Page 255: ...n poll the Timer 1 match capture interrupt pending bit T1CON 0 to detect when a Timer 1 match interrupt pending condition exists T1CON 0 1 When the interrupt request is acknowledged by the CPU and the service routine starts the interrupt service routine for vector F6H must clear the interrupt pending condition by writing a 0 to T1CON 0 Match CTL T1CON 5 T1CON 4 P3 0 R Clear Pending T1CON 0 Interru...

Page 256: ... Buffer Register MUX IRQ1 Clear IRQ1 Match note NOTE Match signal is occurrd only in interval mode T1CON 7 6 T1CON 2 T1CON 3 Match Signal T1OVF Data Bus Timer 1 Data High Low Register CAOF T F F fOSC 16 fOSC 8 fOSC 4 R OVF T1CON 3 T1CON 5 4 T1CON 1 T1CON 0 Figure 11 3 Timer 1 Block Diagram 11 4 ...

Page 257: ... 1 Control Register T1CON FAH Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB Timer 1 Interrupt Pending Bit 0 No interrupt pending 0 Clear pending bit when write 1 Interrupt is pending Timer 1 Interrupt Match capture Enable Bit 0 Disable interrupt 1 Enable interrupt Timer 1 Overflow Interrupt Enable Bit 0 Disable overflow interrupt 1 Enable overflow interrupt Timer 1 Input Clock Selection Bits 00 fOSC 4 ...

Page 258: ...w byte Register T1CNTL F7H Set 1 Bank 0 R 7 6 5 4 3 2 1 0 MSB LSB Reset Value 00H Timer 1 Data High byte Register T1DATAH F8H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB Reset Value FFH Timer 1 Data Low byte Register T1DATAL F9H Set 1 Bank 0 R W 7 6 5 4 3 2 1 0 MSB LSB Reset Value FFH Figure 11 5 Timer 1 Registers T1CNTH T1CNTL T1DATAH T1DATAL 11 6 ...

Page 259: ...r A control register CACON 8 bit down counter with auto reload function Two 8 bit reference data registers CADATAH and CADATAL Counter A has two functions As a normal interval timer generating a counter A interrupt IRQ2 vector ECH at programmed time intervals To supply a clock source to the 16 bit timer counter module Timer 1 for generating the Timer 1 overflow interrupt NOTE The CPU clock should ...

Page 260: ...If a borrow occurs the value of the CADATAH register is loaded into the 8 bit counter However if the next borrow occurs the value of the CADATAL register is loaded into the 8 bit counter Data Bus Counter A Data High Byte Register CACON 0 CAOF Repeat Control CLK DIV 1 DIV 2 DIV 4 DIV 8 CACON 2 fOSC Interrupt Control CACON 4 5 INT GEN To Other Block P3 1 REM CACON 3 CACON 6 7 Figure 12 1 Counter A B...

Page 261: ... 1 T F F is high Counter A Mode Selection Bit 0 One shot mode 1 Repeating mode Counter A Start Stop Bit 0 Stop counter A 1 Start counter A Counter A Input Clock Selection Bits 00 fOSC 01 fOSC 2 10 fOSC 4 11 fOSC 8 Counter A Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt Counter A Interrupt Time Selection Bits 00 Elapsed time for low data value 01 Elapsed time for high data value 10 El...

Page 262: ... 100H where Fx the selected clock When CAOF 1 tLOW CADATAH 2 1 Fx 0H CADATAH 100H where Fx the selected clock tHIGH CADATAL 2 1 Fx 0H CADATAL 100H where Fx the selected clock To make tLOW 24 us and tHIGH 15 us fOSC 4 MHz FX 4 MHz 4 1 MHz Method 1 When CAOF 0 tLOW 24 us CADATAL 2 FX CADATAL 2 x 1us CADATAL 22 tHIGH 15 us CADATAH 2 FX CADATAH 2 x 1us CADATAH 13 Method 2 When CAOF 1 tHIGH 15 us CADAT...

Page 263: ...OF 0 CADATAL 00H CADATAH 00H CAOF 1 CADATAL 00H CADATAH 00H Low Low Counter A Clock 0H CAOF 1 CADATAL DEH CADATAH 1EH CAOF 0 CADATAL DEH CADATAH 1EH CAOF 1 CADATAL 7EH CADATAH 7EH CAOF 0 CADATAL 7EH CADATAH 7EH 100H 200H 20H E0H E0H 20H 80H 80H 80H 80H 100H 200H Figure 12 4 Counter A Output Flip Flop Waveforms in Repeat Mode 12 5 ...

Page 264: ...n frequency is 4 MHz 0 25 μs CADATAH 8 795 μs 0 25 μs 35 18 CADATAL 17 59 μs 0 25 μs 70 36 Set P3 1 C MOS push pull output and CAOF mode ORG 0100H Reset address START DI LD CADATAL 70 2 Set 17 5 ms LD CADATAH 35 2 Set 8 75 ms LD P3CON 11110010B Set P3 to C MOS push pull output Set P3 1 to REM output LD CACON 00000110B Clock Source Fosc Disable Counter A interrupt Select repeat mode for Counter A S...

Page 265: ... 1 C MOS push pull output and CAOF mode ORG 0100H Reset address START DI LD CADATAH 160 2 Set 40 ms LD CADATAL 1 Set any value except 00H LD P3CON 11110010B Set P3 to C MOS push pull output Set P3 1 to REM output LD CACON 00000001B Clock Source Fosc Disable Counter A interrupt Select one shot mode for Counter A Stop Counter A operation Set Counter A Output Flip Flop CAOF high LD P3 80H Set P3 7 Ca...

Page 266: ...COUNTER A S3F80P5_UM_ REV1 00 NOTES 12 8 ...

Page 267: ...k Oscillator frequency fOSC divided by 4 8 or 16 Internal clock input from the counter A module counter A flip flop output You can use Timer 2 in three ways As a normal free run counter generating a timer 2 overflow interrupt IRQ3 vector F0H at programmed time intervals To generate a timer 2 match interrupt IRQ3 vector F2H when the 16 bit timer 2 count value matches the 16 bit value written to the...

Page 268: ...2H whenever a triggering condition is detected at the P3 0 pin for 32 pin package and P3 3 pin for 44 pin package The T2CON 5 and T2CON 4 bit pair setting is used to select the trigger condition for capture mode operation rising edges falling edges or both signal edges In capture mode program software can poll the timer 2 match capture interrupt pending bit T2CON 0 to detect when a timer 2 capture...

Page 269: ...r 2 match capture interrupt pending bit T2CON 0 to detect when a timer 2 match interrupt pending condition exists T2CON 0 1 When the interrupt request is acknowledged by the CPU and the service routine starts the interrupt service routine for vector F2H must clear the interrupt pending condition by writing a 0 to T2CON 0 M atch C TL T2C O N 5 T2C O N 4 P3 0 R C lear Pending T2C O N 0 Interrupt Ena...

Page 270: ... Buffer Register MUX IRQ3 Clear IRQ3 Match note NOTE Match signal is occurrd only in interval mode T2CON 7 6 T2CON 2 T1CON 3 Match Signal T2OVF Data Bus Timer 2 Data High Low Register CAOF T F F fOSC 16 fOSC 8 fOSC 4 R OVF T2CON 3 T2CON 5 4 T2CON 1 T1CON 0 Figure 13 3 Timer 2 Block Diagram 13 4 ...

Page 271: ...imer 2 Control Register T2CON E8H Set 1 Bank 1 R W 7 6 5 4 3 2 1 0 MSB LSB Timer 2 Interrupt Pending Bit 0 No interrupt pending 0 Clear pending bit when write 1 Interrupt is pending Timer 2 Interrupt Match capture Enable Bit 0 Disable interrupt 1 Enable interrupt Timer 2 Overflow Interrupt Enable Bit 0 Disable overflow interrupt 1 Enable overflow interrupt Timer 2 Input Clock Selection Bits 00 fOS...

Page 272: ...w Byte Register T2CNTL E5H Set 1 Bank 1 Read only 7 6 5 4 3 2 1 0 MSB LSB Reset Value 00H Timer 2 Data High Byte Register T2DATAH E6H Set 1 Bank 1 R W 7 6 5 4 3 2 1 0 MSB LSB Reset Value FFH Timer 2 Data Low Byte Register T2DATAL E7H Set 1 Bank 1 R W 7 6 5 4 3 2 1 0 MSB LSB Reset Value FFH Figure 13 5 Timer 2 Registers T2CNTH T2CNTL T2DATAH T2DATAL 13 6 ...

Page 273: ...he chapter 18 S3F80P5 FLASH MCU Flash ROM Configuration The S3F80P5 flash memory consists of 144sectors Each sector consists of 128bytes So the total size of flash memory is 128x144 bytes 18KB User can erase the flash memory by a sector unit at a time and write the data into the flash memory by a byte unit at a time 18Kbyte Internal flash memory Sector size 128 Bytes 10years data retention Fast pr...

Page 274: ...by LDC instruction for the safety of On Board Program Software The ISP sectors are available only when the ISP enable disable bit is set 0 that is enable ISP at the Smart Option If you don t like to use ISP sector this area can be used as a normal program memory can be erased or programmed by LDC instruction by setting ISP disable bit 1 at the Smart Option Even if ISP sector is selected ISP sector...

Page 275: ...ddress 003FH RESET Control Bit 0 External interrupts by P0 and P2 or SED R generate the reset signal 1 External interrupts by P0 and P2 or SED R do not generate the reset signal ISP Reset Vector Address Selection Bits 2 00 200H ISP Area size 256 bytes 01 300H ISP Area size 512 bytes 10 500H ISP Area size 1024 bytes 11 900H ISP Area size 2048 bytes ROM Address 003EH ISP Protection Size Selection Bi...

Page 276: ...rt Option 003EH ISP Size Selection Bit Bit 2 Bit 1 Bit 0 Area of ISP Sector ISP Sector Size 1 x x 0 0 0 0 0 100H 1FFH 256 Bytes 256 Bytes 0 0 1 100H 2FFH 512 Bytes 512 Bytes 0 1 0 100H 4FFH 1024 Bytes 1024 Bytes 0 1 1 100H 8FFH 2048 Bytes 2048 Bytes NOTE The area of the ISP sector selected by smart option bit 3EH 2 3EH 0 can t be erased and programmed by LDC instruction in user program mode ISP RE...

Page 277: ...ion is activated when you set FMCON 0 to 1 If you write FMCON 0 to 1 for erasing CPU is stopped automatically for erasing time min 10ms After erasing time CPU is restarted automatically When you read or program a byte data from or into flash memory this bit is not needed to manipulate FLASH MEMORY USER PROGRAMMING ENABLE REGISTER FMUSR The FMUSR register is used for a safe operation of the flash m...

Page 278: ...e destination address to write data into FMSECH and FMSECL register If the next operation is also to write one byte data user should check whether next destination address is located in the same sector or not In case of other sectors user should load sector address to FMSECH and FMSECL Register according to the sector Refer to page 14 14 PROGRAMMING TIP Programming Flash Memory Sector Address Regi...

Page 279: ...8 byte sizes So the sector to be located destination address should be erased first to program a new data one byte into flash memory Minimum 10ms delay time for the erase is required after setting sector address and triggering erase start bit FMCON 0 Sector erase is not supported in tool program modes MDS mode tool or programming tool Sector 0 9 128 byte x 10 Sector 143 128 byte Sector 142 128 byt...

Page 280: ...Memory Sector Address Register FMSECH and FMSECL FMUSR should be enabled just before starting sector erase operation And to erase a sector Flash Operation Start Bit of FMCON register is written from operation stop 0 to operation start 1 That bit will be cleared automatically just after the corresponding operation completed In other words when S3F80P5 is in the condition that flash memory user prog...

Page 281: ...OP LD FMUSR 00H User program mode disable SB0 s Case2 Erase flash memory space from sector n to sector n m Pre define the number of sector to erase LD SecNumH 00H Set sector number LD SecNumL 128 Selection the sector128 base address 4000H LD R6 01H Set the sector range m to erase LD R7 7DH into High byte R6 and Low byte R7 LD R2 SecNumH LD R3 SecNumL ERASE_LOOP CALL SECTOR_ERASE XOR P4 11111111B D...

Page 282: ...tor MULT RR14 80H The size of one sector is 128 bytes ADD R13 R14 BTJRF FLAGS 7 NOCARRY INC R12 NOCARRY LD R10 R13 LD R11 R15 ERASE_START SB1 LD FMUSR 0A5H User program mode enable LD FMSECH R10 Set sector address LD FMSECL R11 LD FMCON 10100001B Select erase mode enable Start sector erase ERASE_STOP LD FMUSR 00H User program mode disable SB0 RET 14 10 ...

Page 283: ...1000XB 4 Set Flash Memory Sector Address Register FMSECH and FMSECL to the sector base address of destination address to write data 5 Load a transmission data into a working register 6 Load a flash memory upper address into upper register of pair working register 7 Load a flash memory lower address into lower register of pair working register 8 Load transmission data to flash memory location area ...

Page 284: ... User Program Mode Disable FMSECH High Address of Sector FMSECL Low Address of Sector R n High Address to Write R n 1 Low Address to Write R data 8 bit Data LDC RR n R data FMUSR 00H SB0 Mode Select FMCON 01010000B FMUSR 0A5H Select Bank0 Set Address and Data Finish 1 BYTE Writing Figure 14 9 Byte Program Flowchart in a User Program Mode 14 12 ...

Page 285: ...ess to Write R n 1 Low Address to Write R data 8 bit Data LDC RR n R data Mode Select FMCON 01010000B FMUSR 0A5H Select Bank0 Set Address and Data INC R n 1 Same Sector R data New 8 bit Data FMUSR 00H SB0 Finish Writing NO YES NO YES NO YES NO YES User Program Mode Disable Update Data to Write Check Sector Check Address Increse Address Different Data Continuous address Write again Figure 14 10 Pro...

Page 286: ...B0 Case2 Programming in the same sector WR_INSECTOR RR10 Address copy R10 high address R11 low address LD R0 40H SB1 LD FMUSR 0A5H User program mode enable LD FMCON 01010000B Selection programming mode and Start programming LD FMSECH 40H Set the base address of sector located in target address to write data LD FMSECL 00H The sector 128 s base address is 4000H LD R9 33H Load data 33H to write LD R1...

Page 287: ...in target address to write data LD FMSECL 00H The sector 50 s base address is 1900H LD R9 55H Load data 55H to write LD R10 19H Load flash memory upper address into upper register of pair working register LD R11 40H Load flash memory lower address into lower register of pair working register CALL WR_BYTE WR_INSECTOR128 LD FMSECH 40H Set the base address of sector located in target address to write...

Page 288: ...ddress into lower register of pair working register 3 Load receive data from flash memory location area on LDC instruction by indirectly addressing mode PROGRAMMING TIP Reading LD R2 03H Load flash memory s upper address to upper register of pair working register LD R3 00H Load flash memory s lower address to lower register of pair working register LOOP LDC R0 RR2 Read data from flash memory locat...

Page 289: ...d Lock Protection is following that In tool mode the manufacturer of serial tool writer could support Hardware Protection Please refer to the manual of serial program writer tool provided by the manufacturer The program procedure in user program mode 1 Set Flash Memory User Programming Enable Register FMUSR to 10100101B 2 Set Flash Memory Control Register FMCON to 01100001B 3 Set Flash Memory User...

Page 290: ...EMBEDDED FLASH MEMORY INTERFACE S3F80P5_UM_ REV1 00 NOTES 14 18 ...

Page 291: ...s for LVD_FLAG detection LVD LVD circuit supplies two operating modes by one comparator back up mode input and system reset input The S3F80P5 can enter the back up mode and generate the reset signal by the LVD level note1 detection using LVD circuit When LVD circuit detects the LVD level in falling power S3F80P5 enters the Back up mode Back up mode input automatically creates a chip stop state Whe...

Page 292: ...and LVD FLAGn n 1 4 are not overlapped Symbol Min Typ Max Unit LVD_GAP1 150 230 310 mV LVD_GAP2 250 330 410 mV LVD_GAP3 800 880 960 mV LVD_GAP4 1000 1080 1160 mV Symbol Min Typ Max Unit GAP Between LVD_Flag1 and LVD_Flag2 50 100 150 mV GAP Between LVD_Flag2 and LVD_Flag3 500 550 600 mV GAP Between LVD_Flag3 and LVD_Flag4 150 200 250 mV VREF VIN Resistor String Comparator LVD BackupMode Reset Bias ...

Page 293: ... VDD LVD _Flag Voltage 1 VDD LVD _Flag Voltage Not used for S 3F80 P5 Figure 15 2 Low Voltage Detect Control Register LVDCON LOW VOLTAGE DETECTOR FLAG SELECTION REGISTER LVDSEL LVDSEL is used to select LVD flag level The reset value of LVDSEL is 00H Low Voltage Detect Flag Selection Register LVDSEL F1H Set1 Bank 1 R W 7 6 5 4 3 2 1 0 MSB LSB Not used for S3F80P5 LVD Flag Level Selection Bit 00 LVD...

Page 294: ...Supply Voltage in Stop Mode Typical Low Side Driver Sink Characteristics Typical High Side Driver Source Characteristics Stop Mode Release Timing When Initiated by an External Interrupt Stop Mode Release Timing When Initiated by a Reset Stop Mode Release Timing When Initiated by a LVD Input Output Capacitance A C Electrical Characteristics Input Timing for External Interrupts Oscillation Character...

Page 295: ...A Operating Temperature TT A 25 to 85 C Storage Temperature TT STG 65 to 150 C Table 16 2 D C Electrical Characteristics TA 25 C to 85 C VDD 1 60 V to 3 6 V Parameter Symbol Conditions Min Typ Max Unit Operating Voltage VDD FOSC 4MHz 8 MHz 1 60 3 6 V Input High Voltage VIH1 All input pins except VIH2 and VIH3 0 8 VDD VDD V VIH3 XIN VDD 0 3 VDD Input Low Voltage VIL1 All input pins except VIL3 0 0 ...

Page 296: ...2mA Port0 Port1 0 4 1 0 Input High Leakage Current ILIH1 VIN VDD All input pins except ILIH2 and XOUT 1 μA ILIH2 VIN VDD XIN 20 Input Low Leakage Current ILIL1 VIN 0 V All input pins except ILIL2 and XOUT 1 μA ILIL2 VIN 0 V XIN 20 Output High Leakage Current ILOH VOUT VDD All output pins 1 μA Output Low Leakage Current ILOL VOUT 0 V All output pins 1 μA Pull Up Resistors RL1 VIN 0 V VDD 2 35 V TT ...

Page 297: ... pull up resistors or external output current loads 2 IDD1 includes flash operating current flash erase write read operation 3 The adder by LVD on current in back up mode is 18uA Conditions Min Typ Max Unit LVD on current in back up mode VDD 1 60V 18 35 uA Note Back up mode voltage is VDD between LVD and POR Table 16 3 Characteristics of Low Voltage Detect Circuit TA 25 C to 85 C Parameter Symbol ...

Page 298: ...nd LVD_Flag2 50 100 150 mV GAP Between LVD_Flag2 and LVD_Flag3 500 550 600 mV GAP Between LVD_Flag3 and LVD_Flag4 150 200 250 mV Table 16 4 Power On Reset Circuit TA 25 C to 85 C Parameter Symbol Conditions Min Typ Max Unit Power on reset POR Voltage VPOR 0 8 1 1 1 4 V Table 16 5 Data Retention Supply Voltage in Stop Mode TA 25 C to 85 C Parameter Symbol Conditions Min Typ Max Unit Data Retention ...

Page 299: ... 00 Execution of STOP Instrction VDDDR Stop Mode Idle Mode Basic Timer Active Data Retention Mode tWAIT EXT INT VDD Normal Operating Mode 0 2VDD 0 8VDD Figure 16 1 Stop Mode Release Timing When Initiated by an External Interrupt 16 6 ...

Page 300: ...op Mode Release Timing When Initiated by a LVD Table 16 6 Input Output Capacitance TA 25 C to 85 C Parameter Symbol Conditions Min Typ Max Unit Input Capacitance CIN 10 pF Output Capacitance COUT I O Capacitance CIO f 1 MHz VDD 0 V unmeasured pins are connected to VSS Table 16 7 A C Electrical Characteristics TA 25 C to 85 C Parameter Symbol Conditions Min Typ Max Unit Interrupt Input High Low Wid...

Page 301: ...ELECTRICAL DATA S3F80P5_UM_ REV1 00 tINTH tINTL 0 8 VDD 0 2 VDD 0 2 VDD 0 8 VDD NOTE The unit tCPU means one CPU clock period Figure 16 3 Input Timing for External Interrupts Port 0 and Port 2 16 8 ...

Page 302: ... TA 25 C to 85 C Oscillator Clock Circuit Conditions Min Typ Max Unit Crystal XIN C1 C2 XOUT CPU clock oscillation frequency 1 8 MHz Ceramic XIN C1 C2 XOUT CPU clock oscillation frequency 1 8 MHz External Clock XIN XOUT External Clock Open Pin XIN input frequency 1 8 MHz 16 9 ...

Page 303: ...nimum oscillator voltage range 10 ms External clock main system XIN input High and Low width tXH tXL 25 500 ns tWAIT when released by a reset note1 216 fOSC ms Oscillator stabilization wait time tWAIT when released by an interrupt note2 ms NOTES 1 fOSC is the oscillator frequency 2 The duration of the oscillation stabilization time tWAIT when it is released by an interrupt is determined by the set...

Page 304: ...25 C to 85 C Parameter Symbol Conditions Min Typ Max Unit Flash Erase Write Read Voltage Fewrv VDD 1 60 3 3 3 6 V Programming Time note1 Ftp 20 30 μS Sector Erasing Time note2 Ftp1 4 12 mS Chip Erasing Time note3 Ftp2 32 70 mS Data Access Time FtRS VDD 2 0 V 250 nS Number of Writing Erasing FNwe 10 000 Times Data Retention Ftdr 10 Years NOTES 1 The programming time is the time during which one byt...

Page 305: ... Symbol Conditions Min Typ Max Unit HBM 2000 V MM 200 V Electrostatic discharge VESD CDM 500 V NOTE If on board programming is needed it is recommended that add a 0 1uF capacitor between TEST pin and VSS for better noise immunity otherwise connect TEST pin to VSS directly 16 12 ...

Page 306: ...urrently available in a 24 pin SOP and SDIP package NOTE Dimensions are in millimeters 24 SOP 375 10 30 0 30 13 24 1 12 15 74 MAX 15 34 0 20 0 69 0 8 0 15 0 10 0 05 9 53 7 50 0 20 0 85 0 20 0 05 MIN 2 30 0 10 2 50 MAX 0 38 0 10 MAX 0 10 0 05 1 27 Figure 17 1 24 Pin SOP Package Mechanical Data 17 1 ...

Page 307: ...NOTE Dimensions are in millimeters 23 35 MAX 22 95 0 20 1 70 24 SDIP 300 6 40 0 20 24 1 0 46 0 10 0 89 0 10 13 12 0 15 0 2 5 0 1 0 0 0 5 7 62 3 25 0 20 5 08 MAX 1 778 0 51 MIN 3 30 0 30 Figure 17 2 24 Pin SDIP Package Mechanical Data 17 2 ...

Page 308: ... chip CMOS microcontroller is the Flash MCU It has an on chip Flash MCU ROM The Flash ROM is accessed by serial data format NOTE This chapter is about the Tool Program Mode of Flash MCU If you want to know the User Program Mode refer to the chapter 14 Embedded Flash Memory Interface 18 1 ...

Page 309: ... P0 3 INT3 P0 4 INT4 P0 5 INT4 P0 6 INT4 P0 7 INT4 S3C80P5 24 SOP SDIP TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 12 VDD P2 0 INT5 P3 1 REM T0CK P3 0 T0PWM T0CAP T1CAP T2CAP P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 24 23 22 21 20 19 18 17 16 15 14 13 Figure 18 1 Pin Assignment Diagram 24 Pin SOP SDIP Package 18 2 ...

Page 310: ...e 1 If user uses the flash writer tool mode ex spw2 etc user should connect TEST pin to VDD S3F80P5 supplies high voltage 12 5V by internal high voltage generation circuit nRESET nRESET 7 I Chip Initialization VDD VSS VDD VSS 24 1 Power supply pin for logic circuit VDD should be tied to 3 3V during programming NOTE Test Pin Voltage The TEST pin on socket board for OTP MTP writer must be connected ...

Page 311: ...perating mode read write or read protection is selected according to the input signals to the pins listed in Table 22 2 below Table 18 2 Operating Mode Selection Criteria VDD TEST REG nMEM Address A15 A0 R W Mode 3 3 V 3 3 V 0 0000H 1 Flash ROM read 3 3 V 0 0000H 0 Flash ROM program 3 3 V 1 0E3FH 0 Flash ROM read protection NOTE 0 means Low level 1 means High level 18 4 ...

Page 312: ...circuit emulator OPENice i500 and SK 1200 for the S3C7 S3C9 and S3C8 microcontroller families Samsung also offers supporting software that includes debugger an assembler and a program for setting options TARGET BOARDS Target boards are available for all the S3C8 S3F8 series microcontrollers All the required target system cables and adapters are included on the device specific target board TB80PB i...

Page 313: ... RS 232 USB or OPENIce I 500 RS 232 RS 232C USB POD Probe Adapter OTP MTP Writer Block RAM Break Display Block Trace Timer Block SAM8 Base Block Power Supply Block IBM PC AT or Compatible TB80PB Target Board EVA Chip Target Application System Figure 19 1 Development System Configuration 19 2 ...

Page 314: ...nnector 50 1 26 MAIN_MODE EVA_MODE JP1 J3 SCLK nRESET S DAT VDD VSS O N O N 1 1 SW2 3EH SW3 3FH JP10 U1 JP3 S1 JP6 JP8 JP11 JP5 VDDMCU VDD_3 3 VDD_REG Y1 In Circuit Emulator SK 1200 OPENIce I 500 VCC GND 4 1 00 Pin Connecto r Figure 19 2 TB80PB Target Board Configuration NOTES 1 TB80PB should be supplied 3 3V normally So the power supply from Emulator should be set 3 3V for the target board operat...

Page 315: ...ction When using the internal clock source which is generated from Emulator join connector 2 3 and 4 5 pin If user wants to use the external clock source like a crystal user should change the jumper setting from 1 2 to 5 6 and connect Y1 to an external clock source Emulator 2 3 4 5 JP11 12 NOT used for TB80PB NOT connected SW1 Generation low active reset signal to S3F80PB EVA chip Push switch SW2 ...

Page 316: ...S3F80P5_UM_ REV1 00 ELECTRICAL DATA STOP LED This LED is ON when the evaluation chip S3E80PB is in stop mode 19 5 ...

Page 317: ... 2 T0CK P3 3 T1CAP T2CAP P1 2 P1 3 P2 2 INT7 P2 1 INT6 P2 0 INT5 P4 0 P4 1 P4 2 P4 3 P0 7 INT4 P0 6 INT4 P0 5 INT4 P0 4 INT4 P0 3 INT3 P0 2 INT2 P0 1 INT1 SCLK P0 0 INT0 SDAT P4 4 P4 5 P4 6 P1 7 P1 6 P1 4 N C N C N C P4 7 P1 1 P2 6 INT9 CIN2 RESET VDD VSS XOUT XIN 50 Pin DIP Connector Figure 19 3 50 Pin Connector Pin Assignment for User System Target Board 50 Pin DIP Connector User System 50 Pin D...

Page 318: ...mplete system with an OTP MTP programmer In Circuit Emulator for SAM8 family OPENice i500 SmartKit SK 1200 OTP MTP Programmer SPW uni AS pro US pro GW PRO2 8 gang programmer Development Tools Suppliers Please contact our local sales offices or the 3rd party tool suppliers directly as shown below for getting development tools 8 bit In Circuit Emulator AIJI System OPENice i500 TEL 82 31 223 6611 FAX...

Page 319: ...il sales seminix com URL http www seminix com AS pro On board programmer for Samsung Flash MCU Portable Stand alone Samsung OTP MTP FLASH Programmer for After Service Small size and Light for the portable use Support all of SAMSUNG OTP MTP FLASH devices HEX file download via USB port from PC Very fast program and verify time OTP 2Kbytes per second MTP 10Kbytes per second Internal large buffer memo...

Page 320: ...arding OTP MTP programmer Read Program Verify Blank Protection Support Firmware upgrade SEMINIX TEL 82 2 539 7891 FAX 82 2 539 7819 E mail sales seminix com URL http www seminix com GW PRO2 Gang Programmer for OTP MTP FLASH MCU 8 devices programming at one time Fast programming speed 1 2Kbyte sec PC based control operation mode or Stand alone Full Function regarding OTP MTP program Read Program Ve...

Page 321: ...DEVELOPMENT TOOLS S3F80P5_UM_ REV1 00 NOTES 19 10 ...

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