Samsung P560, Service Manual, Page: 159 / 393

4-9
4. Troubleshooting
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POST Code Function Phase Component
0x09
Set in-POST flag in CMOS that indicates we are in POST. If this bit is not
cleared by postClearBootFlagJ (AEh), the TrustedCore on next boot determine
s that the current configuration caused POST to fail and uses default values fo
r configuration. Clear the
LBT Core
0x2B Enhanced CMOS init LBT Core
0xE0 EFI Variable Init LBT Core
0xC1 PEM (Post Error Manager) init LBT Core
0x3B Debug Service Init (ROM Polit) LBT Core
0xDC POST Update Error LBT Core
0x3A Autosize external cache and program cache size for enabling later in POST. LBT Core
0x0B Enable CPU cache. Set bits in cmos related to cache. LBT Core
0x0F Enable the local bus IDE as primary or secondary depending on other drives detected. LBT Core
0x10 Initialize Power Management. LBT Core
0x14
Verify that the 8742 keyboard controller is responding. Send a self-test
command to the 8742 and wait for results. Also read the switch inputs from the
8742 and write the keyboard controller command byte.
LBT Core
0x1A
Initialize DMA command register with these settings:
1. Memory to memory disabled
2. Channel 0 hold address disabled
3. Controller enabled
4. Normal timing
5. Fixed priority
6. Late write selection
7. DREQ sense active
8. DACK sense active low. Initialize
LBT Core
0x22 Reset the keyboard. LBT Core
0x40 Test A20 line LBT Core
0x67 Quick initialization of all Application Processors in a multi-processor system LBT Core
0x32 Compute CPU speed. LBT Core
0x69 Initialize the handler for SMM. LBT Core
0x6B If CMOS is bad, load Custom Defaults from flash into CMOS. If successful, reboot. LBT Core
0x3C
If CMOS is valid, load chipset registers with values from CMOS, otherwise
load defaults and display Setup prompt. If Auto Configuration is enabled,
always load the chipset registers with the Setup defaults (Rel 6.0).
LBT Core
0x3D Load alternate registers with CMOS values LBT Core
0x42 Initialize interrupt vectors 0 thru 77h LBT Core
0x46 Verify the ROM copyright notice LBT Core
0x45 Initialize all motherboard devices. LBT Core
0x49
1. Size the PCI bus topology and set bridge bus numbers.
2. Set the system max bus number.
3. Write a 0 to the command register of every PCI device.
4. Write a 0 to all 6 base registers in every PCI device.
5. Write a -1 to the status register of every PC
LBT Core
0xC6 Initialize note dock LBT Core
0xC5 PnPnd dual CMOS (optional) LBT Core
0x48
Verify that the equipment specified in the CMOS matches the hardware
currently installed. If the monitor type is set to 00 then a video ROM must exist.
If the monitor type is 1 or 2 set the video switchto CGA. If monitor type 3, set
the video switch to m
LBT Core
0xD1 Initialize BIOS stack LBT Core
0xD3 Setup E820h and WAD memory map LBT Core
0x24 Set segment-register addressability to 4 GB LBT Core