Samsung DVD-807K, Service Manual, Page: 82 / 165

Circuit Descriptions
Samsung Electronics 7-17
Because RF signal, external VCO input voltage and VCO control voltage swings terribly at disc halt, PLL ouput
clock changes largely.(PLL not unlock state)
• CH1 : RFIN(DIC1-50, RF Input signal at disc
halt)
• CH2 : VCO control signal (DD1-3, Variable
capacitance diode)
Fig. 7-28
The input voltage of VCO becomes a regular voltage level(approx. 3.59V in Figure) at DVD playback and VCO
outputs PLL clock depending on this control voltage. The input voltage of VCO swings a little and appears as
frequency variation of VCO as much as change amount. As the control voltage of VCO is higher, PLL clock
frequency becomes high.
• CH1 : RFIN(DIC1-50, RF Input signal at disc
playback)
• CH2 : VCO control signal (DD1-3, Variable
capacitance diode)
Fig. 7-29
After the error-correcting process of input RF signal in DIC1 it makes the acknowlegde signal of CH2 LOW and out-
puts data (CH4).
when MPEG decoder(Video, Audio signal process chip) falls the request signal to 0(LOW) and demands data. The
data acknowledge signal of CH2 and data of CH4 are synchronized with BSTCLK(CH3) and outputted. BSTCLK of
CH3 is made by division of 33MHz into 16.
• CH1 : PVSREQ (DIC1-96, Data request signal
from DVD1)
• CH2 : PVSACK (DIC1-93, Output data
acknowledge signal)
• CH3 : BSTCLK (DIC1-94, Output clock)
• CH4 : PVSIN (DIC1-81~84,87~90, Output data)
Fig. 7-30
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