Samsung DVD-807K, Service Manual

Page: 38 / 165

IC Descriptions
6-27 Samsung Electronics
N A M E
res.
S P
A P
L L C 1
V
S S 1
V
D D 1
R C V 1
R C V 2
M P 7
M P 6
M P 5
M P 4
M P 3
M P 2
M P 1
M P 0
V
D D 2
V
S S 2
RTCI
V D D
1 2 C
S A
V
S S A 1
R(Cr)
C
V
D D A 1
G(Y)
V B S
V
D D A 2
B(Cb)
C V B S
V
D D A 3
V
S S A 2
V
S S A 3
X T A L
X T A L 1
I/O
I
I
I
I
I
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
I
O
O
I
O
O
I
I
I
O
I
PIN
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
3 4
3 5
F U N C T I O N
reserved pin, do not connect
Test Pin;connected to digital ground for normal operation
Test Pin;connected to digital ground for normal operation
Line-Locked Clock input;this is the 27 MHz master clock
digital supply ground 1
digital supply 1
digital supply voltage 2
digital ground 2
Real Time Control input. If the LLC1 clock is provided by an SAA7111 or SAA7151B,
RTCI should be connected to the RTCO pin of the respective decoder to improve the
signal quality.
Sense input for 12C bus voltage;connect to 12C bus supply
Select 12C address; low selects slave address 88h, high selects slave address 8Ch.
Analog ground 1 for Red (Cr), C(CVBS), Green(Y) outputs
Analog ground 3 for the DAC reference ladder and the oscillator
Crystal oscillator output
Crystal oscillator input; if the oscillator is not used, this pin should be connected to
ground.
Analog output of Red (Cr)signal
Analog output of Chrominance (CVBS) signal
Analog supply voltage 1 for R(Cr), C(CVBS) outputs
Analog output of Green(Y) signal
Analog output of VBS (CVBS) signal
Analog supply voltage 2 for VBS(CVBS), Green(Y) outputs
Analog output of Blue(Cb) signal
Analog output of CVBS(CSYNC) signal
Analog supply voltage 3 for Blue(Cb)and CVBS(CSYNC), outputs
Analog ground 2 for VBS (CVBS), Blue(Cb), CVBS(CSYNC)outputs
Raster Contral 1 for video port. This pin receives/provides a VS/FS/FSEQ signal.
Raster Contral 2 for video port. This pin provides an HS pulse of programmable length
or receives an HS pulse.
Double speed 54 MHzMPEG port. It is an input for ¡ CCIR 656 ¡–style multiplexed Cb, Y,
Cr data. Data are sampled on the rising and falling clock edge;data sampled on the
risting edge then are sent to the encoding part of the device, data sampled on the
falling edge are sent to the RGB part of the device.(or vice verse, depending on
programming)
PIN ASSIGNMENT