rtd WLAN17202ER, User Manual

Page: 11 / 17

WLAN17202ER User's Manual 6 RTD Embedded Technologies, Inc.
PCI Bus Signal Description
Address and Data
AD[31:00] Address and Data are multiplexed on the same PCI pins. A bus transaction
consists of an address phase followed by one or more data phases.
C/BE[3:0]# Bus Command/Byte Enables are multiplexed. During the address phase of a
transaction, they define the bus command. During the data phase, they are used
as byte enables.
PAR Parity is even parity across AD[31:00] and C/BE[3:0]#. Parity generation is
required by all PCI signals.
Interface Control Pins
FRAME# Cycle Frame is driven by the current master to indicate the beginning of an
access and will remain active until the final data cycle.
TRDY# Target Ready indicates the selected device’s ability to complete the current data
phase of the transaction. Both IRDY# and TRDY# must be asserted to terminate a
data cycle.
IRDY# Initiator Ready indicates the bus master's ability to complete the current data
phase of the transaction.
STOP# Stop indicates the current selected device is requesting the master to stop the
current transaction.
DEVSEL# Device Select , when actively driven, indicates the driving device has decoded its
address as the target of the current access.
IDSEL Initialization Device Select is used as a chip-select during configuration read
and write transactions.
LOCK# Lock indicates an atomic operation to a bridge that may require multiple
transactions to complete.
Error Reporting
PERR# Parity Error is for reporting data parity errors.
SERR# System Error is for reporting address parity errors.
Arbitration (Bus Masters Only)
REQ# Request indicates to the arbitrator that this device desires use of the bus.
GNT# Grant indicates to the requesting device that access has been granted.
System
CLK Clock provides timing for all transactions on the PCI bus and is an input to every
PCI device.
RST# Reset is used to bring PCI-specific registers, sequencers, and signals to a
consistent state.
M66EN 66 MHz Enable indicates to a device whether the bus segment is operating at 33
MHz or 66 MHz. The PCI bus has been simulated at 33MHz. For the purpose of
this specification, 66MHz is not supported. To support future enhancements, the
M66EN signal should be grounded on any module that cannot support 66MHz and
left open for modules that can support a 66MHz clock.
Interrupts
INTA# Interrupt A is used to request Interrupts.
INTB# Interrupt B is used to request Interrupts.
INTC# Interrupt C is used to request Interrupts.
INTD# Interrupt D is used to request Interrupts.