ML7404 Family LSIs
Hardware Design Manual
FEXL7404DG-03
1
1. Placing decoupling capacitors
Place decoupling capacitors between each power pins and GND as shown in Figure 1.1.
Figure 1.1 Power Supply Block Diagram
*[1] The supply voltage for the PA_OUT pin (#20) should be provided the DC bias through the inductor (L3)
REG_PA(#21)
VDD_PA(#22)
VDD_REG(#1)
Including backside GND
GND
REG_OUT(#3)
PA_OUT(#20)
VBG(#2)
PA
VDD
REG_CORE(#4)
VB_EXT(#31)
VDD_VCO(#32)
VDD_CP(#27)
VDD_RF(#25)
Each decoupling capacitors as close to an LSI pin as possible.
PA regulator
VDDIO(#9)
1.5V regulator
Logic circuit
0.1µF
0.1µF
1000pF
1000pF
1000pF
0.1µF
L3*[1]
1000pF
0.1µF
1
μF
0.01uF
1µF
0.1uF
