BU94603KV Functional Specifications
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Target Spec 0.12
Figure V.11.1 I2C start, stop, repeated start condition
V.11.2 Slave address
An I2C bus slave address corresponds to the 7-bit addressing mode. As shown in Table V.11.2, you can
select the slave address using input of A0 terminal and A1 terminal. Figure V.11.2 shows the slave
address transfer format.
Figure V.11.2 Slave Address Transfer Format
Table V.11.2 Settable Slave Addresses
MSB
A6
A5
A4
A3
A2
A1
terminal
LSB
A0
terminal
1
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
0
1
1
V.11.3 Write protocol from master
To send a master command using an I2C bus, follow the transfer protocol shown in Figure V.11.3. For
details on each command, see Chapter VI.
Figure V.11.3 Command send protocol
V.11.4 Read protocol to master
To send reception data using an I2C bus from the slave to the master, follow the transfer protocol shown
in Figure V.11.4.1. First, transfer the status read command (step1). Then, input SCL clock of required
bytes in step 2 to read the status.
When the device is BUSY at reception of device status or memory data, the I2C bus may possibly be
occupied by the device during BUSY. This LSI transfers the bus to the master so as not to generate such
bus occupation. However, as a BUSY state still exists inside of the system, appropriate data may not be
transferred during BUSY. Therefore, the first byte of transfer data (Step2) is used to judge the transfer
data is enabled/disabled. When specifying addresses from the master to the slave and the first byte of
the transfer data immediately after data transfer is required is 0x00, transfer data from the slave is
enabled. If the first byte is 0xFF, it shows the BUSY state. Therefore, the transfer data should be
disabled. If this happens, retry command transfer at Step 1 to read out the status.
Figure V.11.4.2 shows the relationship between the transfer data and BUSY.
* For further information on BUSY, see Chapter V.17.
MSB
1
2
8
LSB
ACK
9
1
ACK
9
SDA
SCL
Start or
Repeated start
condition
Stop or
Repeated start
condition
S
A6
A5
A4
A3
A2
A1
A0
R/W
ACK
Start
condition
Slave Address
sent by
slave
R / W = Read / Write Pulse
ACK = Acknowledge
S
Slave Address
A
Data(8bit)
R/W
A
Data(8bit)
A
Data(8bit)
P
A/A
From Master to Slave
From Slave to Master
"0"(write)
A = Acknowledge(SDA low)
A = No Acknowledge(SDA high)
S = Start Condition
P = Stop condition
