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BU7893GU

 

SAMPLE#    AUDIO PATH+ AUDIO DAC BLOCK SETTING SEQUENCE 
 

After powering up and canceling reset, set paths according to the sequence shown as below: 
(1) Start up reference voltage 

Start up the reference voltage in the REF_PWR register (00h). 

To start up the VREF block fast, set the REF_ON bit (bit-0) and BST_ON bit (bit-1) to "1" simultaneously.    After starting 
up the reference voltage startup, set just the BST_ON bit (bit-1) to "0". 

 

(2) Start up Audio DAC 

When using Audio DAC 

(2-1) Enable PLL block clock input and start up PLL 

 

 

Start up the power supply of the PLL and enable clock input to the PLL in the PLL_PWR 

        register (16h). 

 

 

Set REF1_ON (bit-1) and PLL_ON (bit-0) to "1" simultaneously. 

(2-2) Caution concerning interim between starting up PLL block and starting up Audio DAC block 

After starting up the power supply of the PLL in the PLL_PWR register (16h), wait 10 msec before starting up the 
Audio DAC. 

(2-3) Start up Audio DAC block 

 

 

Start up the power supply of the Audio DAC in the DAC SET4 register (13h). 

 

 

Set DAC_ON (bit-5) and DAC_RSTB (Bit-4) to "1". 

(2-4) Set 3D surround and Equalyzer parameter 

Please tell us about the parameter setting when you use this function. 

 

(3) Start up analog input amplifier to use 

Start up the power supply of the input amplifier and input volume in the IAMP_PWR register (01h). 

 
(4) Set input volume 

Set the input volume in the IVR_1 register (09h). 

 
(5) Set mixing path 

Make mixing path settings in the MIX1 register (02h), MIX2 register (03h), MIX3 register (04h), and MIX4 register (05h). 

 
(6) Set startup noise reduction sequence 

Set the sequence time in the POP_TM register (07h). 

 
(7) Set click noise reduction sequence 

Set the sequence time in the OVR_TM register (0Ah). 
 

(8) Set output path 

Enable the relevant output path in the PATH_CNT register (06h). 

 
(9) Set output volume 

Set output volume values =0x18(-48dB) in the OVR_1 register (0Bh). 

 

(10) Ramp up output driver amplifier 

Ramp up the output driver amplifier in the DRV_PWR register (08h). 
 

(11) Caution concerning interim between ramping up output driver amplifier and canceling mute 

After setting the DRV_PWR register (08h), wait the sequence time set in the POP_TM register (07h) before canceling 
mute. 
 

(12) Cancel mute 

Cancel mute state of the output driver amplifier in the DRV_MT register (0Ch). 
 

(13) Caution concerning interim between canceling mute and setting output volume 

After setting the DRV_MT register (0Ch), wait the sequence time that is set in the OVR_TM register (0Ah) before 
subsequently setting output volume. 

 
(14) Set output volume 

Set output volume values in the OVR_1 register (0Bh). 

Summary of Contents for BU7858KN

Page 1: ...orrective circuit in headphone amplifier 5 Volume that can adjust the gain 6 Flexible mixing function APPLICATION Portable information communication equipments such as cellular phone and PDA Personal...

Page 2: ...1 8 1 98 V ELECTRICAL CHARACTERISTICS BU7858KN Unless otherwise specified Ta 25 AVDD DVDD 3 0V Analog Parameter Symbol Min Typ Max Unit Condition Current Consumption Idd3 2 3 3 7 mA 16 driver part and...

Page 3: ...urrent 2 Digital melody IDDA2 6 0 10 0 mA SDI MIX1 SPOL SDI MIX2 SPOR TCXOI 19 8MHz fs 44 1kHz DC Characteristic Parameter Termin al Symbol Min Typ Max Unit Condition L Output Voltage Vold All output...

Page 4: ...e Level MLHP 90 80 dB 1kHz BPF HPL_V Volume Setting 1 GA1HPL 48 0 dB 2dB step HPL_V Volume Setting 2 GA2HPL 42 6 dB 2dB step HPR_V Volume Setting 1 GA1HPR 48 0 dB 2dB step HPR_V Volume Setting 2 GA2HP...

Page 5: ...UT SIGNAL FREQ FIN Hz THD N dB 0 01 0 10 1 00 10 00 100 00 100 80 60 40 20 0 INPUT LEVEL VIN dBV THD N 0 01 0 10 1 00 10 00 100 00 100 80 60 40 20 0 INPUT LEVEL VIN dBV THD N 0 01 0 10 1 00 10 00 100...

Page 6: ...16bit D A Converter Total Harmonic Distortion SPOL Fig 21 16bit D A Converter Total Harmonic Distortion SPOR Fig 22 Headphone Amplifier Total Harmonic Distortion HPOL HPOR Fig 23 Speaker Preamp Total...

Page 7: ...R CSTEP LPF LPF RXI HP_L HP_R ATT2 MIX SEL1 EXTO MIX SEL2 MIX SEL3 MIX SEL4 MEL_L EXTI 600 16 16 ATT1 MCLKI ATT3 SW1 SW2 Serial Control CA_L CA_R CSTART ATT5 MCLKO PLLC PLL ATT4 ATT ATT BCLK SP Amp SP...

Page 8: ...c Stereo Analog Interface From Melody LSI Serial I F 19 2MHz 19 68MHz 19 8MHz 6800p 8 16 1 F 0 1 F SPOL SP Amp 8 HPOR CCR RX EXT DACR VOL 6800p 16 SPOR DACR DACR EXT RX EXT SIO SO COMOUT COMIN SP Amp...

Page 9: ...r nearest DVSS of IC in order to reduce the noise interference Then it is possible to monitor the master clock that is generated internally from MCLKO which is after all the monitor terminal and hence...

Page 10: ...2 f CCHPx 100 k the maximum low band boost is 6dB For parameter setting determine the output coupling capacitance CL and the headphone impedance RL before calculating the low band cut off frequency f...

Page 11: ...of NCS H between first Byte and Second Byte because it is not compatible with continuous data transmission For the following th please wait the time more than 1 SCLK Clock th tcyc Fig 33 CPU I F Timi...

Page 12: ...ode 2 SO_ENABLE bit0 at register address 14h 1 SIO SCLK SEL DT 7 DT 6 DT 0 DT 1 SO Output data AD 6 AD 5 AD 4 AD 0 Direction L DT 5 Hi Z Hi Z Tsd Fig 34 CPU I F Timing Chart BU7893GU DVDD_IO 1 62 3 3V...

Page 13: ...interpreted as the control signal START STOP Conditions When SIO and SCLK are H there is no data transfer performed on the I2 C bus A HIGH to LOW transition on the SIO line while SCLK is HIGH is one...

Page 14: ...direction of data transfer Afterwards data from incremented addresses is read The register addresses are incremented after transfer completion Compound writing is possible by writing R W 0 after resen...

Page 15: ...K I Audio DAC LR Clock DVDD A 3 BCLK I Audio DAC BIT Clock DVDD A 4 DVDD Digital Power Supply 5 DVSS Digital Ground DVDD 6 SCLK I Serial Clock for CPU Interface DVDD A 7 SDATA I Serial Data for CPU In...

Page 16: ...Output AVDD H 20 SPO O Line Output for Speaker AVDD H 21 EXTI I External Input AVDD D 22 MEL_L I Melody Input L ch AVDD D 23 MEL_R I Melody Input R ch AVDD D 24 RING I RING Input AVDD E 25 RXI I RXI I...

Page 17: ...LC I O Capacitor Connection Terminal for PLL Loop Filter AVDD L 16 E4 DVDD_CORE Digital Core Power Supply DVDD_CORE 17 F3 DVDD_IO Digital IO Power Supply DVDD_IO 18 B3 DVSS Digital Ground DVDD_IO DVDD...

Page 18: ...24 PAD A IN Schmitt Trigger PAD B IN PAD IN C PAD D IN PAD INOUT E PAD INOUT F Schmitt Trigger PAD IN G PAD OUT H PAD IN I PAD OUT J PAD IN OUT K PAD L IN OUT Fig 37 Equivalent Circuit Diagrams BU7893...

Page 19: ...PDN 1 Using PLL DAC Setting Using DAC DAC MUTE OFF Using DAC HPAMP RESET Lifting Using HPAMP Power Supply OFF RESET NRST 0 or PLLPDN 0 VCOM 0 HPAMP RESET HPRST 0 Analog Power OFF PDN 0 PLL OFF PLLPDN...

Page 20: ...up analog input amplifier to use Start up the power supply of the input amplifier and input volume in the IAMP_PWR register 01h 4 Set input volume Set the input volume in the IVR_1 register 09h 5 Set...

Page 21: ...Cancel mute Cancel output mute in the DRV_MT register 0Ch POWER DOWN SEQUENCE 1 Set output volume Set output volume values 0x18 48dB in the OVR_1 register 0Bh 2 Caution concerning interim between set...

Page 22: ...trong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them 8 Inspection with set PCB On the inspection with the set PCB if a capacitor is connected to...

Page 23: ...d reel on the left hand and you pull out the tape on the right hand Tape Quantity Direction of feed Embossed carrier tape with dry pack 2500pcs E2 Tape and Reel information When you order please order...

Page 24: ...Catalog No 07T253A 07 10 ROHM...

Page 25: ...l bear no re sponsibility whatsoever for any dispute arising from the use of such technical information The Products specified in this document are intended to be used with general use electronic equi...

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