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7/8 

 

z

 Operation Notes 

1 .  Absolute maximum range 

Absolute Maximum Ratings are those values beyond which the life of a device may be destroyed. We cannot be defined the failure mode, 
such as short mode or open mode. Therefore a physical security countermeasure, like fuse, is to be given when a specific mode to be 
beyond absolute maximum ratings is considered. 

2 . GND potential 

GND terminal should be a lowest voltage potential every state. 

Please make sure all pins, which are over ground even if, include transient feature. 

3 . Electrical Characteristics 

Be sure to check the electrical characteristics that are one the tentative specification will be changed by temperature, supply voltage, and 
external circuit. 

4 .  Bypass Capacitor for Noise Rejection 

Please put into the capacitor of 1µF or more between VDD

 

pin and GND, and the capacitor of about 1000pF between VOUT pin and GND, to 

reject noise. If extremely big capacitor is used, transient response might be late. Please confirm sufficiently for the point. 

5 .  Short Circuit between Terminal and Soldering 

Don’t short-circuit between Output pin and VDD pin, Output pin and GND pin, or VDD pin and GND pin. When soldering the IC on circuit 
board, please be unusually cautious about the orientation and the position of the IC. When the orientation is mistaken the IC may be 
destroyed. 

6 . Electromagnetic Field 

Mal-function may happen when the device is used in the strong electromagnetic field. 

7 .    The VDD line inpedance might cause oscillation because of the detection current. 
8 .    A VDD -GND capacitor (as close connection as possible) should be used in high V

DD

 line impedance condition. 

9 .    Lower than the mininum input voltage makes the V

OUT

 high impedance, and it must be V

DD

 in pull up (V

DD

) condition. 

10.    This IC has extremely high impedance terminals. Small leak current due to the uncleanness of PCB surface might cause unexpected 

operations. Application values in these conditions should be selected carefully. If the leakage is assumed between the VOUT terminal and 
the GND terminal, the pull-up resistor should be less than 1/10 of the assumed leak resistance. 

11. External parameters 

The recommended parameter range for RL

 

is 10k

1M

. There are many factors (board layout, etc) that can affect characteristics. 

Please verify and confirm using practical applications. 

12. Power on reset operation 

  Please note that the power on reset output varies with the VDD rise up time. Please verify the actual operation.   

13. Precautions for board inspection 

Connecting low-impedance capacitors to run inspections with the board may produce stress on the IC. Therefore, be certain to use 

proper discharge procedure before each process of the test operation. 

To prevent electrostatic accumulation and discharge in the assembly process, thoroughly ground yourself and any equipment that could 

sustain ESD damage, and continue observing ESD-prevention procedures in all handing, transfer and storage operations. Before 
attempting to connect components to the test setup, make certain that the power supply is OFF. Likewise, be sure the power supply is 
OFF before removing any component connected to the test setup. 

14. When the power supply, is turned on because of in certain cases, momentary Rash-current flow into the IC at the logic unsettled, the 

couple capacitance, GND pattern of width and leading line must be considered. 

 
 
 

Part Number Selection 

B D 4           

 

 T R 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Standard CMOS Reset IC 

Reset Voltage Value Package 

Taping 

Specifications 

BD48: Open Drain Type 

23: 2.3V 

G: SSOP5 

Embossed Taping 

BD49: CMOS Output Type 

to (0.1V step) 

FVE: VSOF5 

 

 60: 

6.0V 

 

 

 
 
 
 

Summary of Contents for BD48**FVE Series

Page 1: ...D4940 EU 5 8V BD4858 DV 3 9V BD4839 GU 5 8V BD4958 FV 3 9V BD4939 ET 5 7V BD4857 DU 3 8V BD4838 GT 5 7V BD4957 FU 3 8V BD4998 ES 5 6V BD4856 DT 3 7V BD4837 GS 5 6V BD4956 FT 3 7V BD4937 ER 5 5V BD4855...

Page 2: ...VS T 100 ppm Ta 40 to 105 Designed Guarantee Hysteresis Voltage VS VS 0 03 VS 0 05 VS 0 08 V VS 1 1V RL 470k VDD L H L Circuit Current at ON IDD1 0 66 1 98 A VDD VS 0 2V VS 5 3 6 0V Circuit Current a...

Page 3: ...V S V BD4842G FVE Low to High VS VS High to Low VS Fig 9 Circuit Current when ON 0 0 0 5 1 0 1 5 40 20 0 20 40 60 80 100 TEMPERATURE Ta CIRCUIT CURRENT WHEN ON I DD1 A BD4842G FVE Fig 10 Circuit Curre...

Page 4: ...ationship between the input voltages VDD and the output voltage VOUT when the input power supply voltage VDD is made to sweep up and sweep down the circuits are those in Fig 12 and 13 When the power s...

Page 5: ...o the VOUT pin the reset signal input terminal of the microcontroller please take into account the waveform of the rise and fall of the output voltage VOUT 2 The following is an example of a circuit a...

Page 6: ...A voltage drop of the through current I1 input resistor R2 is caused by the through current and the input voltage to descends when the output switches from Low to High When the input voltage decrease...

Page 7: ...UT high impedance and it must be VDD in pull up VDD condition 10 This IC has extremely high impedance terminals Small leak current due to the uncleanness of PCB surface might cause unexpected operatio...

Page 8: ...of the same implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by ROHM CO LTD is granted to any such buyer T...

Page 9: ...this document are no antiradiation design Appendix1 Rev2 0 Thank you for your accessing to ROHM product informations More detail product informations and catalogs are available please contact your nea...

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