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Reference Data
Examples of Leading (TPLH) and Falling (TPHL) Output
Part Number
TPLH (µs)
TPHL (µs)
BD4845G/FVE 39.5
87.8
BD4945G/FVE 32.4
52.4
VDD=4.3V
→
5.1V VDD=5.1V
→
4.3V
*
This data is for reference only.
The figures will vary with the application, so please confirm actual operating conditions before use.
●
Explanation of Operation
For both the open drain type (Fig. 12) and the CMOS output type (Fig. 13), the detection and release voltages are used as threshold voltages.
When the voltage applied to the VDD pins reaches the applicable threshold voltage, the VOUT terminal voltage switches from either “High” to
“Low” or from “Low” to “High”. Because the BD48
□□
G/FVE series uses an open drain output type, it is possible to connect a pull-up resistor to
VDD or another power supply [The output “High” voltage (VOUT) in this case becomes VDD or the voltage of the other power supply].
Fig.12 (BD48
□□
Type Internal Block Diagram)
Fig.13 (BD49
□□
Type Internal Block Diagram)
●
Timing Waveform
Example: the following shows the relationship between the input voltages VDD and the output voltage VOUT when the input power supply
voltage VDD is made to sweep up and sweep down (the circuits are those in Fig. 12 and 13).
①
When the power supply is turned on, the output is unsettled from after
over the operating limit voltage (VOPL) until TPHL. There fore it is
possible that the reset signal is not outputted when the rise time of
VDD is faster than TPHL.
②
When VDD is greater than VOPL but less than the reset release
voltage (VS +
∆
VS), the output voltages will switch to Low.
③
If VDD exceeds the reset release voltage (VS +
∆
VS), then
VOUT
switches from L to H.
④
If VDD drops below the detection voltage (VS) when the power supply
is powered down or when there is a power supply fluctuation, VOUT
switches to L (with a delay of TPHL).
⑤
The potential difference between the detection voltage and the release
voltage is known as the hysteresis width (
∆
VS). The system is
designed such that the output does not flip-flop with power supply
fluctuations within this hysteresis width, preventing malfunctions due to
noise.
Vref
R1
R2
V
DD
GND
Q1
V
OUT
R3
R
L
Vref
R1
R2
R3
Q2
Q1
V
DD
V
OUT
GND
V
DD
V
DET
+
Δ
V
DET
V
DET
V
OPL
0V
T
PHL
①
②
V
OUT
T
PLH
T
PHL
T
PLH
③
④
V
OL
V
OH
⑤
Fig.14
