15
DS8241-03 January 2014
www.richtek.com
RT8241
©
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
and T
A
is the ambient temperature. The junction to ambient
thermal resistance,
θ
JA
, is layout dependent. For WQFN-
12L 2x2 packages, the thermal resistance,
θ
JA
, is 165
°
C/
W on a standard JEDEC 51-3 single-layer thermal test
board. The maximum power dissipation at T
A
= 25
°
C can
be calculated by the following formula :
P
D(MAX)
= (125
°
C
−
25
°
C) / (165
°
C/W) = 0.606W for
WQFN-12L 2x2 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance,
θ
JA
. For the RT8241 package, the derating
curve in Figure 8 allows the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
Figure 8.
Derating Curves for the RT8241 Package
Layout Considerations
Layout is very important in high frequency switching
converter design. If designed improperly, the PCB could
radiate excessive noise and contribute to converter
instability. For best performance of the RT8241, the
following guidelines should be strictly followed.
`
Connect an RC low-pass filter from VCC, (1
μ
F and 10
Ω
are recommended). Place the filter capacitor close to
the IC.
`
Keep current limit setting network as close as possible
to the IC. Routing of the network should be kept away
from high voltage switching nodes to prevent it from
coupling.
`
Connections from the drivers to the respective gate of
the high side or the low side MOSFET should be as
short as possible to reduce stray inductance.
`
All sensitive analog traces and components pertaining
to FB, GND, EN, PGOOD, CS and VCC should be
placed away from high voltage switching nodes such as
PHASE, LGATE, UGATE, or BOOT nodes to prevent it
from coupling. Use internal layer(s) as ground plane(s)
and shield the feedback trace from power traces and
components.
`
Current sense connections must always be made using
Kelvin connections to ensure an accurate signal, with
the current limit resistor located at the device.
`
Power sections should connect directly to ground
plane(s) using multiple vias as required for current
handling (including the chip power ground connections).
Power components should be placed to minimize loops
and reduce losses.
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0
25
50
75
100
125
Ambient Temperature (°C)
M
ax
imu
m
P
ow
er
Di
ss
ipa
ti
on
(W
)
1
Four-Layer PCB
