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CCT24
The average full-duplex serial port byte rate that can be supported under error free conditions is:
64 Bytes/4.85 ms = 13.2 kB/s, or 132 kb/s for 8N1
Continuous full-duplex serial port data streams at a baud rate of 115.2 kb/s can be supported by this
configuration, provided only occasional RF transmission errors occur. Plan on an average serial port data
flow of 90% of the calculated error-free capacity for general-purpose applications.
The CCT24 transmit and receive buffers hold at least 1024 bytes and will accept brief bursts of data at
high baud rates, provided the average serial port data flow such as shown in the example above is not
exceeded. It is strongly recommended that the CCT24 host use hardware flow control in applications
where the transmit buffer can become full. The host must send no more than 32 additional bytes to the
CCT24 when the CCT24 de-asserts the host’s CTS line. In turn, the CCT24 will send no more than one
byte following the host de-asserting its RTS line. Three-wire serial port operation is allowed through
parameter configuration, as discussed in Section 4.2.4. However, data loss is possible under adverse RF
channel conditions when using three-wire serial operation due to buffer overruns.
2.14 SPI Port Operation
The CCT24 SPI port data rate is configurable in 127 steps from 6.35 to 80.64 kb/s using the
SPI_ Divisor
parameter. The SPI data rate is the clocking rate the CCT24 uses in Master mode. The SPI data rate is
also used in Slave mode to time SPI Select (/SS) sampling, etc. Where possible, devices connected to
the CCT24 SPI port should be configured to match the 80.64 kb/s data rate. In any event, the SPI data
rate used by the CCT24 and the connected device should be matched within a few percent for efficient
data transfers. SPI port operation is full duplex in the sense that a single clock signal simultaneously
shifts data into and out of the SPI port. In order for the Master (host) to receive data from a CCT24 SPI
Slave, it must clock bytes into the CCT24.
As show in Figure 2.14.1, CCT24 SPI slave mode operation is supported by two control signals from the
CCT24. The /HOST_CTS line provides the same flow control function for SPI Slave mode as it does for
the serial (UART) port. The Master (host) can clock messages into the CCT24 SPI Slave whenever
/HOST_ CTS is set to a logic low state. The Master can complete clocking one protocol formatted mes-
sage into the CCT24 if /HOST_CTS switches high part way through the message as shown in Figure
2.14.2, but must then stop sending transmit message bytes until the CCT24 resets /HOST_CTS to a logic
low state. If the CCT24 slave is holding a received message(s) when the SPI master clocks in a message
to transmit, received message bits will be simultaneously clocked out on the MISO line while the message
to be transmitted is clocked in on the MOSI line. The end of a received message will often not be aligned
with the end of a message to be transmitted, so additional clocking may be required to complete the
transfer of a received message(s). It is acceptable to clock 0x00 null bytes in on the MOSI line to retrieve
received message bytes when /HOST_CTS is high, but not transmit message bytes.
