TONiC RKLC20-S linear installation guide
14
Alarm asserted when:
– Signal amplitude <20% or >135%
– Readhead speed too high for reliable operation
E− output only for Ti options A, B, C, D
or 3-state alarm
Differentially transmitted signals forced open
circuit for >15 ms when alarm conditions valid.
Output specifications
Digital output signals
Form – Square wave differential line driver to EIA RS422A (except limits P and Q)
Analogue output signals
Incremental 2 channels V
1
and V
2
differential sinusoids in quadrature centred on 1.65 V
(90° phase shifted)
NOTE: Ti0000A00V centred on 2.5 V
Bi-directionally repeatable
Differential pulse V
0
centred on 45
°
Reference
20 µm
45°
(V
1
+)−(V
1
−)
(V
2
+)−(V
2
−)
(V
0
+)−(V
0
−)
0.8 to 1.2 Vpp
360° (nominal)
0°
Alarm
Asynchronous pulse
Line driven
Limits Open collector output, asynchronous pulse
Digital Ti interfaces only
Limits Open collector output, asynchronous pulse
Ti0000 interface only
Repeatability <0.1 mm
Length of limit actuator
V
p
V
q
T103
x
readhead only
Active low
V
p
V
q
Repeatability <0.1 mm
Length of limit actuator
Active high
Repeatability
<0.1 mm
Length of limit actuator
P Q
Active high
or
Active low
P Q
Repeatability
<0.1 mm
Length of limit actuator
Incremental
2 channels A and B in quadrature (90° phase shifted)
Reference
NOTE: Select ‘standard’ or ‘wide’ reference at time of ordering, to match the requirements of the controller being used.
Wide reference mark not available on Ti0004 interfaces.
Signal period
Resolution
A
B
Z
Z
Bi-directionally repeatable pulse Z, duration equal to the resolution
Bi-directionally repeatable pulse Z, duration equal to the signal period
Wide reference
Set-up*
Voltage
at V
X
3.3 (nom)
50%
70%
100%
0
0
Signal level
Between 50% and 70% signal level, V
X
is a duty cycle, 20 µm duration.
Time spent at 3.3 V increases with incremental signal level.
At >70% signal level V
X
is nominal 3.3 V.
E
>15 ms
Set-up*
0
Voltage
at X
1
100%
0
Signal level
Set-up signal voltage proportional to incremental signal amplitude
NOTE: Ti0000 interface contains a transistor to invert the readhead’s ‘active low’ signal to give an ‘active high’ output.
*
Set-up signals as shown are not present
during calibration routine.
Inverse signals not shown for clarity
NOTE: No limits on TD interfaces. P limit becomes E+ for options E, F, G, H.
0.7 to 1.35 Vpp with Green LED indication,
(readhead) and 120R termination.
Differential signals V
0
+ and V
0
− centred on ~1.65 V
NOTE: Ti0000A00V centred on 2.5 V