*Notice: The information in this document is subject to change without notice
Tsi301
Notes
Tsi301 HyperTransport to PCI User Manual
5-36
Secondary Bus Number
Offset 19h
Bits
Type
Reset
Description
7:0
RW
00h
Secondary Bus Number - PCI bus number of the bus which the HyperTransport
PCI bridge sources. Not persistent through warm reset.
Subordinate Bus Number
Offset 1Ah
Bits
Type
Reset
Description
7:0
RW
00h
Subordinate Bus Number - PCI bus number of the highest numbered bus
behind the HyperTransport PCI bridge. Not persistent through warm reset.
Secondary Latency Timer
Offset 1Bh
Bits
Type
Reset
Description
7:0
RW
00h
Timer - controls how long the HyperTransport PCI bridge may continue to
occupy the PCI once the arbiter has taken the grant away in PCI clocks. The
bottom two bits are hard wired to 0. Not persistent through warm reset.
I/O Base Address
Offset 1Ch
Bits
Type
Reset
Description
7:4
RW
0h
Address - bits 15:12 of the base of the I/O range. 11:0 are assumed to be 0,
leading to a 4 KB granularity. Not persistent through warm reset.
3:0
R
1h
Addressing Capability - indicates the size of I/O addresses supported by the
device, indicates 32 bits.
I/O Limit Address
Offset 1Dh
Bits
Type
Reset
Description
7:4
RW
0h
Address - bits 15:12 of the top of the I/O range. 11:0 are assumed to be 1, lead-
ing to a 4 KB granularity. Not persistent through warm reset.
3:0
R
1h
Capability - indicates the size of I/O addresses supported by the device, 32 bits.