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*Notice: The information in this document is subject to change without notice

2-6

Notes

Chapter 2 Signal Descriptions

2.1 HyperTransport Signals

Note:

The Lx_ prefix denotes signals associated with either HyperTransport Link 0 (x=0) or Hyper-

Transport Link 1 (x=1).

The PCI bridge HyperTransport implementation is a standard HyperTransport design. Table 2.1 lists all

HyperTransport signals. For details on the characteristics of these signals, refer to the

Lightning Data Trans-

port I/O Link Protocol Specification, Revision 1.0

and the

Lightning Data Transport Electrical Specification,

Revision 0.77

, both

from AMD.

2.2 PCI Signals

The HyperTransport PCI bridge implements a standard PCI interface, as detailed in

PCI Local Bus Specifi-

cation, Revision 2.2

. Table 2.2 lists all HyperTransport PCI bridge PCI signals.

Signal Name

I/O Type

Signal Type

Lx_RX_CLK_H/L

Input

HyperTransport

Lx_RX_CTL_H/L

Input

HyperTransport

Lx_RX_CAD[7:0]_H/L

Input

HyperTransport

Lx_TX_CLK_H/L

Output

HyperTransport

Lx_TX_CTL_H/L

Output

HyperTransport

Lx_TX_CAD[7:0]_H/L

Output

HyperTransport

Lx_VLDT[2:0]

Power

1.2 volt

L_TSTRST_N

Input

2.5 volt LVCMOS

L_POWER_OK

Input

2.5 volt LVCMOS

L_RST_N

Input

2.5 volt LVCMOS

Table 2.1 HyperTransport Bridge Signals

Signal

Name

I/O Type

Signal Type

P_CBE_N[7:0]

Bidirectional

PCI

P_AD[63:0]

Bidirectional

PCI

P_PAR

Bidirectional

PCI

P_SERR_N

Input

PCI

P_PERR_N

Bidirectional

PCI

P_LOCK_N

Bidirectional

PCI

P_STOP_N

Bidirectional

PCI

P_DEVSEL_N

Bidirectional

PCI

P_TRDY_N

Bidirectional

PCI

Table 2.2 HyperTransport Bridge PCI Signals

Summary of Contents for Tsi301 HyperTransport

Page 1: ... Valley Road San Jose California 95138 Telephone 800 345 7015 408 284 8200 FAX 408 284 2775 Printed in U S A 2009 Integrated Device Technology Inc Tsi301 HyperTransport to PCI User Manual 80D3000_MA001_02 September 2009 ...

Page 2: ...MPLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR THAT IS CONTAINED ON ANY IDT INTERNET SITE IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT CONSEQUENTIAL INCIDENTAL INDIRECT PUNITIVE OR SPECIAL DAMAGES HOWEVER THEY MAY ARISE AND EVEN IF IDT HAS BEEN PREVIOUSLY ADVISED ABOUT THE POSSIBILITY OF SUCH DAMAGES The code examples also may be subject to United States export control laws and ma...

Page 3: ...ons describe the intended audience scope and the organization of this reference manual Audience This reference manual is intended for system designers and others who design using the HyperTransport PCI bridge or who evaluate computer systems based on this chip Scope This manual describes the features requirements and configurations for the HyperTransport PCI bridge including functional and physica...

Page 4: ...to the register Data The following list defines data terminology Quantities A word W is two bytes 16 bits A doubleword DW is four bytes 32 bits A quadword QW is eight bytes 64 bits Abbreviations The following notation is used for bits and bytes Kilo K as in 4 Kbyte page 210 Mega M as in 4 Mbits sec 220 Giga G as in 4 Gbytes of memory space 230 Little Endian Convention The byte with the address xx ...

Page 5: ... Memory Write Invalid NDA Non disclosure Agreement NMI Non maskable Interrupt ORC Outbound Request Controller OS Operating System PBGA Plastic Ball Grid Array PCB Printed Circuit Board PIO Programmed Input Output PCI Peripheral Component Interconnect PLL Phase Locked Loop SBGA Super Ball Grid Array SDRAM Synchronous Direct Random Access Memory SE Single ended SIP Serial Initialization Packet SPD S...

Page 6: ... Notice The information in this document is subject to change without notice About This Manual Notes Tsi301 HyperTransport to PCI User Manual 6 ...

Page 7: ...ort links which allow the connection of multiple bridge chips in a daisy chain configuration Each HyperTransport link has an 8 bit DDR transmit and an 8 bit DDR receive port running at clock speeds up to 400 MHz allowing for raw bandwidth of 800 MB s simultaneously in each direction With protocol over head the maximum sustainable bandwidth in one direction is approximately 705 MB s For testing or ...

Page 8: ...refetch per read of 128 DW Prefetching may be done once at the beginning of each read or it may be enabled to continuously issue requests as data is drained to PCI All prefetch data is discarded when the read disconnects on the PCI bus The bridge chip provides buffer space for a total of 256 DW of read prefetch data 1 3 3 PCI Arbiter The HyperTransport PCI bridge implements an on chip two level PC...

Page 9: ...N can be used in the same way or the PCI bus frequency can be changed without resetting the HyperTransport PCI bridge To support changing the PCI bus frequency without resetting the HyperTransport PCI bridge REFCLK_H L must always run at 33 MHz and P_M66EN must indicate 33 MHz at the rising edge of L_PWROK The clock frequency to the PCI devices and P_M66EN can then be switched between 33 and 66 MH...

Page 10: ... Notice The information in this document is subject to change without notice Tsi301 Notes Tsi301 HyperTransport to PCI User Manual 1 10 ...

Page 11: ...ndard PCI interface as detailed in PCI Local Bus Specifi cation Revision 2 2 Table 2 2 lists all HyperTransport PCI bridge PCI signals Signal Name I O Type Signal Type Lx_RX_CLK_H L Input HyperTransport Lx_RX_CTL_H L Input HyperTransport Lx_RX_CAD 7 0 _H L Input HyperTransport Lx_TX_CLK_H L Output HyperTransport Lx_TX_CTL_H L Output HyperTransport Lx_TX_CAD 7 0 _H L Output HyperTransport Lx_VLDT 2...

Page 12: ...50_PCI 7 0 is at 3 3 V PCI signals conform to the PCI 3 3 V signalling rules If AP_TYPEDET_N is pulled high and VDD3050 PCI 7 0 is at 5 0 V PCI signals conform to the PCI 5 0 V signalling rules No other combinations of AP_TYPEDET_N and VDD3050 PCI 7 0 are supported P_IRDY_N Bidirectional PCI P_FRAME_N Bidirectional PCI P_REQ64_N Bidirectional PCI P_ACK64_N Bidirectional PCI P_PAR64 Bidirectional P...

Page 13: ...ignal is not available in Pass2 Customers should use the BLKx_INT y signals instead Note In Pass1 if this pin is not needed for an interrupt it can be floated or pulled to 2 5 volts SMI_N Bidirectional In Pass1 2 5 volt LVCMOS In Pass2 this signal is absent System Management Interrupt Signal This signal is not available in Pass2 Customers should use the BLKx_INT y signals instead Note In Pass1 if ...

Page 14: ...nput In Pass1 2 5 volt LVCMOS In Pass2 3 3 volt LVCMOS In Pass1 this is a reserved input and can be left floating or pulled to GND In Pass2 this is the JTAG clock input TDI Pass1 output Pass2 input In Pass1 2 5 volt open drain LVCMOS In Pass2 3 3 volt open drain LVCMOS In Pass1 this is a reserved output and not guaranteed to be quiet In Pass2 this is the JTAG data input TDO Output In Pass1 2 5 vol...

Page 15: ...alf of a differential pair or it can be tied to a reference voltage REFCLK_PLL_BYPASS Input 2 5 volt LVCMOS When this signal is asserted the PLL is bypassed REFCLK_H L input pins are used directly to drive internal clocks REFCLK_PLL_VCC This is the 2 5 V power input for the PLL REFCLK_PLL_GND This is the ground input for the PLL 2 7 Core and I O Power Signals VDD Core power 2 5 V VSS Ground VDDQ_A...

Page 16: ...rator Logic Signals Lx_RREF_GND Lx_RREF Bidirectional These signals are used by the HyperTransport calibrator logic A resistor should be placed between these two pins The resistor value should be equal to half of the differential impedance of the HyperTransport signals which is 100 ohms 10 Note The LDT_RREF_GND should not be connected to ground ...

Page 17: ...aves and the host Direct peer to peer communication is not allowed To support peer to peer operations packets are reflected through the host Packets issued from the host to a HyperTransport slave are defined to travel downstream on the HyperTransport chain Packets issued from a HyperTransport slave to the host are defined to travel upstream Intermediate nodes in the daisy chain forward packets fro...

Page 18: ...ffer Allocation Each virtual channel always needs at least one data buffer allocated to it to prevent deadlock A data buffer is considered allocated to a virtual channel if it has been released to that channel and is awaiting data or if it has received data but has not yet been retired Two types of user specified data buffer allocation are allowed Guaranteed buffers specified in the NeedPReq NeedN...

Page 19: ...fall is setting a channel s Want values so high that it prevents buffers from being available to the other channels inadvertently throttling performance Figure 3 3 Data Buffer Life Cycle 3 2 2 Packet Decode As packets are placed in the Rx buffers the associated commands and addresses are decoded to deter mine whether the HyperTransport PCI bridge is the packet target on the HyperTransport chain Th...

Page 20: ...port Address Map HyperTransport implements a single flat 40 bit address space for all accesses All address spaces that can be reached from HyperTransport are mapped into this space The HyperTransport PCI bridge checks addresses on incoming packets in each space for subranges that it accepts 3 3 1 Memory Mapped Space The HyperTransport specification places Memory Mapped Space in the address range o...

Page 21: ...Transport PCI bridge The output stream is combined with the stream of packets forwarded through the HyperTransport PCI bridge from the far HyperTransport link receiver s Rx buffers This later multiplexing is also used to insert NOP buffer release messages to the transmitter on the link s other end Packet transmission is paced by the transmit buffer counters maintained in each virtual channel for b...

Page 22: ... at their destinations that fact is signaled back to the ORC which allows the request buffer to be retired If the request was nonposted the transaction will require generation of a response to the host OCR considers posted transactions as complete when the request completes at its destination and the buffer is retired Nonposted transactions are complete when the response packet is issued to the Hy...

Page 23: ...lding 48 DW of data 16 DW each for three HyperTransport read requests Because multiple reads may be in progress to the PCI and CSR interfaces at one time with their returning data getting interleaved by PCI disconnects this cannot be a FIFO structure Each buffer accumulates data for its request until all requested DW are returned This data is then combined with response header informa tion from th...

Page 24: ...n bit in the Command CSR is set Configuration and Special Cycles The HyperTransport PCI bridge never acts as a target for configuration or special cycles on the PCI bus 3 6 2 PCI Posted Write Queue The HyperTransport PCI bridge responds as a PCI write target to PCI Memory Write Memory Write Invali date and I O Write commands All of these writes are posted to the HyperTransport chain The HyperTrans...

Page 25: ... and adding a leading 0 zero bit If three or four delayed request buffers are in use a maximum of four reads may be outstanding for each one The subrequest number is two bits The delayed request buffer number is two bits If only one or two delayed request buffers are in use a 3 bit subrequest number is used Only one bit of delayed request buffer number is needed and the top bit is dropped Either w...

Page 26: ...re is an ideal prefetch count for large transfers The ideal prefetch count is determined by dividing the number of bytes that can be transferred on the PCI bus in the round trip read latency by 64 the number of bytes in a prefetch request The number of bytes that can be transferred on the PCI bus depends on the bus characteristics 32 or 64 bit 33 or 66 MHz or 25 or 50 MHz Round trip read latency d...

Page 27: ... PCI Arbiter The HyperTransport PCI bridge includes a PCI arbiter This arbiter is an independent unit The Hyper Transport PCI bridge internal PCI request and PCI grant signals connect to pins as P_REQ_OUT_N and P_GNT_IN_N It is possible to either use this arbiter or to bypass it and use an external arbiter The HyperTransport PCI bridge arbiter contains two round robin arbitration groups P_REQ0_N a...

Page 28: ...ER_OK internal SIP values are used for all configuration bits and no data is loaded 3 8 4 Reset Configuration In addition to loading configuration information from the SIP information may also be loaded into the HyperTransport PCI bridge at reset from the PCI AD bus P_AD 63 0 Signal I O Definition minRstCnt P_AD 31 Reserved for API NetWorks Must be tied to 0 dbgSelCtl P_AD 30 Use SROM or CSR for d...

Page 29: ...ut changing any fields causes initialization of the master host bit This indicates the HyperTransport link that connects toward the host bridge Polling the error bits for that link determines whether the node on the far end is detecting any fatal errors on the link If so this link is not to be used fabric sizing is complete and you can proceed to Step 5 2 Software reads the Class Code Vendor ID an...

Page 30: ... the requester s responsibility to take appropriate action on receipt of the error Transmission of HyperTransport error responses without NXA sets the SigdTgtAbort bit in the Status CSR Transmission of a target abort on PCI sets the SigdTgtAbort bit in the Secondary Bus Status CSR Errors may be signaled to the system by the error interrupt pins Two pins FATAL_ERR_N and NONFATAL_ERR_N allow divisio...

Page 31: ... has traversed the whole chain If the outgoing packet was not a nonposted request either posted request or response or a broadcast then there is no in band way to signal the error The packet is dropped and may be signaled as an error as shown in Table 3 3 Master Errors The HyperTransport PCI bridge accepts received responses that match its unitId and compares the response srcTags to the bridge s o...

Page 32: ...span more than one 32 bit block receive HyperTransport error responses equiv alent to a PCI target abort No other action is taken Error responses may also be signaled to HyperTransport because of errors taken when the request was issued to PCI 3 11 PCI Errors 3 11 1 PCI System Errors PCI devices may assert an unrecoverable system error by asserting SERR on the secondary PCI bus Settings for this e...

Page 33: ...nsferred at the time of the error and in which direction the transfer was occurring Table 3 7 indicates the CSR bits used to log and enable reporting of each PCI parity error The HyperTransport PCI bridge may also sample P_PERR_N asserted when it is driving write data out indicating that a parity error was detected by the target of the write If the ParErrRespEn bit is set and the request was a non...

Page 34: ...metric nandtree test mode There are three different nandtrees HyperTransport I Os the output is DBGOUT2 PCI I Os the output is P_REQ_OUT_N Any other signals the output is DBGCLK A version of the HyperTransport nandtree output that provides a pulse every time the HyperTransport nandtree output changes is output on TDO This allows some characterization of the speed of the chip Note In Pass2 there is...

Page 35: ...s clock at the same frequency Sixteen interrupt pins are used as the inputs to the scan chains and 16 PCI AD pins are used as the outputs of the scan chains See Table 3 8 for details on how to enable internal scan mode Scan outputs are provided on P_AD 24 9 and scan inputs are given on the BLK3_IRQ 3 0 BLK2_IRQ 3 0 BLK1_IRQ 3 0 BLK0_IRQ 3 0 signals Note In Pass2 scan outputs are on DBGOUT 19 0 DBG...

Page 36: ... Notice The information in this document is subject to change without notice Tsi301 Notes Tsi301 HyperTransport to PCI User Manual 3 20 ...

Page 37: ...ble 4 1 are the HyperTransport frequency per wire The actual HyperTransport data rate is 2 times the rate of this frequency 4 2 Clock Features 4 2 1 Definitions coreClk MHz Lx_TX_CLK_H L MHz REFCLK_H L MHz coreClkSel Lx_clkSel P_M66EN 100 200 25 01 001 0 100 200 50 01 001 1 100 400 25 01 000 0 100 400 50 01 000 1 133 200 33 00 001 0 133 200 66 00 001 1 133 400 33 00 000 0 133 400 66 00 000 1 Table...

Page 38: ...packet on the link to the clock edge where the Rx Sync FIFO captures the doubleword of data 3 LDT Rx Clock data alignment factor Note For an 8 byte header the two 4 byte halves can be received aligned so that they are received by the core in the same core clock cycle or unaligned split across two core clock cycles For headers received aligned there is an additional delay defined as the data alignm...

Page 39: ...ng the minimum forward path idle latency through the HyperTransport PCI bridge is HyperTransport Rx PHY delay Rx Sync FIFO delay HyperTransport Link I F delay logic delay forwarding HyperTransport Link I F delay Tx Sync FIFO delay HyperTransport Tx PHY delay The calculation is 3 LDT Rx Clock 2 Core Clock 2 Core Clock 0 Core Clock 2 Core Clock 1 Core Clock 1 LDT Tx Clock 3 2 5 7 7 5 1 75 2 5 7 5 52...

Page 40: ...nimum insertion path idle latency through the HyperTransport PCI bridge is PCI I F delay Application logic delay PCI insertion HyperTransport Link I F delay Tx Sync FIFO delay HyperTransport Tx PHY delay The calculation is 4 PCI Clock 3 Core Clock 2 Core Clock 2 Core Clock 1 75 LDT Tx Clock 4 15 7 7 5 1 75 2 5 60 52 5 4 4 116 9 ns Note Data Alignment Factor and Clock Alignment Factor do not apply ...

Page 41: ... Notice The information in this document is subject to change without notice Tsi301 Notes Tsi301 HyperTransport to PCI User Manual 4 6 ...

Page 42: ... Notice The information in this document is subject to change without notice Tsi301 Notes Tsi301 HyperTransport to PCI User Manual 4 6 ...

Page 43: ...rizes the HyperTransport PCI bridge configuration register offsets devices default values after reset and access types 5 1 1 Register Access Definitions Access types are indicated as follows R ReadA read of this register returns the field W WriteA write of this register loads the value T ToggleA write of 1 to this field toggles the value S SetA write of 1 to this field sets the field C ClearA writ...

Page 44: ... 13 31h 30h I O Range Base Upper 16 Bits 0000h 14 33h 32h I O Range Limit Upper 16 Bits 0000h 14 34h Capability 1 40h 14 3Bh 38h Expansion ROM 00000000h 14 3Ch Interrupt Line FFh 14 3Dh Interrupt Pin 00h 14 3Fh 3Eh Bridge Control 0000h 15 40h HyperTransport Capability ID 08h 16 41h Capability 2 00h 16 43h 42h HyperTransport Command 0020h 17 45h 44h HyperTransport Link 0 Control 0000h 17 47h 46h Li...

Page 45: ... Interface 0 Tx From SROM 29 8Fh 8Ch Serial ROM SROM Interface 1 From SROM 29 93h 90h Serial ROM SROM Interface 1 Rx From SROM 29 97h 94h Serial ROM SROM Interface 1 Tx From SROM 29 9Bh 98h Serial ROM SROM Interface Control From SROM 30 BFh A0h Interrupt Controllers 30 C1h C0h Special Interrupts FEDCh 31 C2h Interrupt Diagnostics 00h 31 C3h Interrupt Block Level 0 00h 32 C4h Interrupt Block Level ...

Page 46: ...t Upper 32 Bits 2Ch I O Range Limit Upper 16 Bits I O Range Base Upper 16 Bits 30h Reserved Capability 1 34h Expansion ROM 38h Bridge Control Interrupt Pin Interrupt Line 3Ch HyperTransport Command Capability 2 HyperTransport Capability ID 40h Link 0 Width Control HyperTransport Link 0 Control 44h Link 1 Width Control HyperTransport Link 1 Control 48h Reserved Link Freq 1 Link Freq 0 HyperTranspor...

Page 47: ...Level 0 Interrupt Diagnostics Special Interrupts C0h Interrupt Special Block Interrupt Block Level 3 Interrupt Block Level 2 Interrupt Block Level 1 C4h Reserved Transmit Buffer Counter Maximum 0 C8h Reserved Transmit Buffer Counter Maximum 1 CCh Reserved D0h Debug D4h Reserved Space HyperTransport Diagnostics D8h Diagnostics Link 0 Receive CRC Expected DCh ECh EFh are Reserved Diagnostics Link 0 ...

Page 48: ... 0 Reserved always reads 0 9 R 0 FastB2BEn this has no meaning for HyperTransport Always reads 0 8 RW 0 SerrEn this enables system error interrupt pins FATAL_ERR_N and NONFATAL_ERR_N to be driven 0 SERR_N output driver disabled default 1 SERR_N output driver enabled Not persistent through warm reset 7 R 0 WaitCycCtrl this has no meaning for HyperTransport Always reads 0 6 R 0 ParErrRespEn controls...

Page 49: ...e 1 Respond to memory space accesses Not persistent through warm reset 0 RW 0 IoSpaceEn controls the bridge s response as a target to I O space transac tions on the primary interface If clear the bridge does not accept any requests within the I O space LDT FD_FC00_0000 FD_FDFF_FFFF range 0 Disable I O space 1 Respond to I O space accesses Not persistent through warm reset Status Offset 07h 06h Bit...

Page 50: ... for HyperTransport Always reads 01 Note In Pass1 DEVSEL_N Timing always reads 00 8 R 0 PCI Parity Error Detected this bit is used to report the detection of a parity error by the bridge when it is the master of the transaction HyperTransport doesn t have parity errors 7 R 0 Fast Back to Back Capability this is not meaningful for HyperTransport Always reads 0 6 R 0 Reserved always reads 0 5 R 0 66...

Page 51: ...ne all byte enables asserted generate MemWrInv commands Note In Pass1 CacheLine Size always reads 0 Primary Latency Timer Offset 0Dh Bits Type Reset Description 7 0 R 00h Primary Latency Timer this is not used by the HyperTransport PCI bridge Always reads 0 Header Type Offset 0Eh Bits Type Reset Description 7 0 R 01h Type a value of 01h indicates that this is a bridge header BIST Offset 0Fh Bits T...

Page 52: ...Timer controls how long the HyperTransport PCI bridge may continue to occupy the PCI once the arbiter has taken the grant away in PCI clocks The bottom two bits are hard wired to 0 Not persistent through warm reset I O Base Address Offset 1Ch Bits Type Reset Description 7 4 RW 0h Address bits 15 12 of the base of the I O range 11 0 are assumed to be 0 leading to a 4 KB granularity Not persistent t...

Page 53: ...ough warm reset 0 No target abort received 1 Transaction aborted by target 11 RC 0 Signaled Target Abort this bit reports the signaling of a target abort termination by the bridge when it responds as the target of a transaction on its secondary interface It may be cleared by writing a 1 to it Persistent through warm reset 10 9 R 01 DEVSEL_N Timing encodes the timing of the secondary interface s DE...

Page 54: ...dge supports 64 bit addressing indicated by an encoding of 1h Prefetchable Memory Range Limit Address Offset 27h 26h Bits Type Reset Description 15 4 RW 000h Address bits 31 20 of the top inclusive of the prefetchable memory range Bits 19 0 are assumed to be 0 leading to a 1 MB granularity Not persistent through warm reset 3 0 R 1h Cap indicates whether the bridge supports 32 or 64 bit addressing ...

Page 55: ...s Offset 2Fh 2Ch Bits Type Reset Description 31 8 R 000000h Reserved the HyperTransport PCI bridge does not support decode of address bits above bit 39 Not persistent through warm reset 7 0 RW 00h Address bits 39 32 of the prefetchable memory range limit Memory accesses above 1012 GB will not be accepted regardless of the setting of this register Not persistent through warm reset ...

Page 56: ...t PCI bridge does not support decode of address bits above 24 8 0 RW 000h Address bits 24 16 of the I O range limit Not persistent through warm reset Capability 1 Offset 34h Bits Type Reset Description 7 0 R 40h Pointer register number of the base of the first capabilities block There is only one capability block which is for HyperTransport Expansion ROM Offset 3Bh 38h Bits Type Reset Description ...

Page 57: ...t through warm reset 0 count 215 PCI clocks 1 count 210 PCI clocks 8 R 0 PrimDiscardTimer not meaningful for HyperTransport Always reads 0 7 RW 0 FastB2BEn enables the generation of fast back to back transactions when the HyperTransport PCI bridge is the master on the PCI bus Not persistent through warm reset 6 RW 0 SecBusReset if written to a 1 hardware will perform a reset sequence on the second...

Page 58: ...irst 64KB of PCI I O space If this bit is set it will block forwarding these addresses from the primary to the secondary bus and cause forwarding of these addresses from the secondary to the primary bus regardless of the contents of the IoBase and IoLimit registers Not persistent through warm reset 1 RW 0 SerrEn this bit controls forwarding of system errors from the secondary inter face to the pri...

Page 59: ... Error this bit is set whenever a response or posted write is dropped due to hitting end of chain It can be cleared by writing a 1 to it Persistent through warm reset 13 RC 0 Overflow Error this bit is set whenever an overflow error is detected It may be cleared by writing a 1 to it Persistent through warm reset 12 RC 0 Protocol Error this bit is set whenever a protocol error is detected It may be...

Page 60: ...ble if set this bit causes CRC errors to be treated as fatal errors When detected they will cause all HyperTransport links from this device to be flooded with sync packets and the LinkFail bit to be set Not persis tent through warm reset 0 R 0 Reserved Link 0 Width Control Offset 47h 46h Bits Type Reset Description 15 R 0 Reserved 14 12 R 000b Out this controls the used width of the outgoing link ...

Page 61: ...d always be set prior to setting the XmitOff bit It may only be set by software not cleared It may only be cleared by a warm or cold reset sequence on HyperTransport 6 RS 0 End Of Chain this bit indicates that this link is not part of the logical Hyper Transport chain and that this device should be considered the end of the chain for packets coming from the other direction Packets directed toward ...

Page 62: ... 11 R 0 Reserved 10 8 R 000b In this controls the used width of incoming link to this device It must match the used outgoing width of the device on the other end of the link 000b 8 bit 001b 16 bit 011b 32 bit The HyperTransport PCI bridge only supports 8 bit links 7 R 0 Reserved 6 4 R 000b Max Out indicates the maximum width of the outgoing link supported by this device 000b 8 bit 001b 16 bit 011b...

Page 63: ...1111 at cold reset If SIP is used the register reads 1111 at cold reset If the register comes up 0000 at cold reset software can write it to either 0000 or 0010 and go through warm reset to switch between 200 and 400 MHz opera tion All other encodings are reserved and can lead to undefined behavior Each 4 bit field contains one of the following values 0000 200 MHz 0010 400 MHz 1111 Vendor specifie...

Page 64: ...ead from HyperTransport creating a moving prefetch window Otherwise prefetching will end when the specified number of lines has been fetched Not persistent through warm reset 9 8 RW 00b PCI Delayed Requests this controls the number of PCI delayed requests that may be outstanding at one time The value in the register plus 1 is the number that will be allowed enabling from one to four buffers Not pe...

Page 65: ...before asserting P_FRAME_N Not persistent through warm reset Error Control Offset 67h 64h Bits Type Reset Description 31 R 0 Reserved 30 RC 0 PCI Command Address Parity Error a parity error was detected on the PCI bus during the address phase This is only logged if the Parity Error Response Enable bit in the Bridge Control register is set Not persistent through warm reset 29 RC 0 Master Posted PCI...

Page 66: ...rupt assertion if enabled by SerrEn in the Command register see Command Offset 05h 04h on page 6 Not persistent through warm reset 18 RW 0 Post Fatal Enable if asserted PCI master posted writes that fail to complete successfully on the bus result in a fatal interrupt assertion if enabled by SerrEn in the Command register see Command Offset 05h 04h on page 6 Not persistent through warm reset 17 RC ...

Page 67: ...sport response hitting the end of the HyperTransport chain causes a fatal interrupt Not persistent through warm reset 5 RW 0 Overflow Error Sync Flood Enable if asserted detection of an HyperTransport receive buffer overflow error causes sync flooding and sets the LinkFail bit Not persistent through warm reset 4 RW 0 Overflow Error Nonfatal Enable if asserted detection of an HyperTransport receive...

Page 68: ...t channel Not persistent through warm reset 0 1 RW 01b NeedResp the minimum data buffer allocation to the response channel Not persistent through warm reset HyperTransport Transmit Control Offset 6Eh 6Eh Bit Type Reset Description 7 4 R 0h Reserved 3 0 RW 4h BufRelSpace controls the throttling of buffer release messages on a busy bus If the bus is idle buffer releases always get issued immediately...

Page 69: ...11 RW 0 RxSel enables use of CSR receive impedance values Not persistent through warm reset 10 6 RW 00h TxUp impedance value for transmit pull up resistor Used when TxSel is set Not persistent through warm reset 5 1 RW 00h TxDown impedance value for transmit pull down resistor Used when TxSel is set Not persistent through warm reset 0 RW 0 TxSel enables use of CSR transmit impedance values Not per...

Page 70: ...ro reduce the number of zeros in Sync Sequence 18 R Values come from SROM Sync Pointer Control use Rx Sync Pointer Control 17 15 R Values come from SROM Tx Initial Offset initial Pointer Offset for Tx HyperTransport FIFO Pointers 14 10 R Values come from SROM Rx Margin HyperTransport Receive Pointer margin 9 5 R Values come from SROM Tx Denom denominator value for Tx HyperTransport Clock ratio 4 0...

Page 71: ...reduce the number of zeros in Sync Sequence 18 R Values come from SROM Sync Pointer Control use Rx Sync Pointer Control 17 15 R Values come from SROM Tx Initial Offset initial Pointer Offset for Tx HyperTransport FIFO Pointers 14 10 R Values come from SROM Rx Margin HyperTransport Receive Pointer margin 9 5 R Values come from SROM Tx Denominator denominator value for Tx HyperTransport Clock ratio ...

Page 72: ...alues come from SROM Reserved always reads 0 BlockxInterrupty Offsets BFh A0h Bits Type Reset Description 15 RW 0 Interrupt Enable Not persistent through warm reset 0 Disabled 1 Enabled 14 RW 0 Destination Mode Not persistent through warm reset 0 Physical 1 Logical 13 6 RW FFh Destination ID 8 bit physical mask or logical ID interpreted by host bridges Not persistent through warm reset FF Broadcas...

Page 73: ...ot persistent through warm reset 7 6 RW 11b NMI Message Type Not persistent through warm reset 00 NMI 01 Startup 10 ExtInt 11 Disabled 5 4 RW 01b NMI Vector lower two bits of NMI interrupt vector Not persistent through warm reset 3 2 RW 11b SMI Message Type Not persistent through warm reset 00 NMI 01 Startup 10 SMI 11 Disabled 1 0 RW 00b SMI Vector lower two bits of the SMI interrupt vector Not pe...

Page 74: ...ion 7 R 0b Reserved always reads 0 6 RW 0b Block Enable indicates that the current group is being used Not persistent through warm reset 5 0 RW 000000b Block Vector upper vector bits for Block 0 interrupts Not persistent through warm reset Interrupt Block Level 1 Offset C4h Bits Type Reset Description 7 R 0b Reserved always reads 0 6 RW 0b Block Enable indicates that the current group is being use...

Page 75: ...rupts Interrupt Special Block Offset C7h Bits Type Reset Description 7 R 0b Reserved always reads 0 6 RW 0b Block Enable indicates that the current group is being used Not persistent through warm reset 5 0 RW 000000b Block Vector upper vector bits Not persistent through warm reset Transmit Buffer Counter Maximum Count0 Offset CAh C8 Bits Type Reset Description 3 0 RW Fh PCmd posted command buffer ...

Page 76: ... D4h Bits Type Reset Description 31 28 R 0 Reserved 27 RW 0 Interrupt Debug Enable Not persistent through warm reset 26 24 RW 011b Interrupt Debug Select Not persistent through warm reset 23 18 RW 110010b Select 3 select for Debug Port 3 Not persistent through warm reset Bits 18 20 Pass1 Level 1 MUX select 8 1 Pass2 Reserved Bit 21 0 Rx 1 Tx Bit 22 0 Port 0 1 Port 1 Bit 23 0 Core Debug 1 HyperTran...

Page 77: ...cription 7 5 R 0 Reserved 4 RW 1 Broadcast broadcast enable bit for CSR read commands If cleared to 0 Slave ID bits 3 0 is used If set read data is combined from all sources Not persis tent through warm reset 3 0 RW 0 Slave ID slave ID for CSR read commands Used to specify a particular inter nal CSR slave module to read from Not persistent through warm reset Diagnostics Link 0 Receive CRC Expected...

Page 78: ...e is undefined at power up Diagnostics Link 0 Receive CRC Received Offset F3h F0h Bits Type Reset Description 31 0 R Received CRC value for Link 0 This register is for software use and will survive cold and warm reset as long as there is no power off Diagnostics Link 1 Receive CRC Received Offset F7h F4h Bits Type Reset Description 31 0 R 0 Expected CRC value for Link 0 This register is for softwa...

Page 79: ...er products The information contained herein is provided without representation or warranty of any kind whether express or implied including but not limited to the suitability of IDT s products for any particular purpose an implied warranty of merchantability or non infringement of the intellectual property rights of others This document is presented only as a guide and does not convey any license...

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