Renesas S3A1, User Manual

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Target Board Kit S3A1 (TB-S3A1) Hardware Layout
R12UM0022EU0100 Rev.1.00 Page 24 of 36
Feb 6, 2018
4.5.4 Pin header J4
Pin header J4 is a 2-column by 20-row through-hole header on 0.100 inch centers.
Table 15 Pin Header J4 pin assignment
144p
S3A1 Pin S3A1 Signal J4 Pins S3A1 Signal
144p
S3A1 Pin
12 P704 1 2 P313 47
11 P703 3 4 P202 46
10 P702 5 6 P203 45
9 P701 7 8 P603 95
8 P700 9 10 P610 85
2 P401 11 12 P609 84
1 P400 13 14 P608 83
143 P512 15 16 P303 69
138 P002 17 18 P412 31
135 P005 19 20 P808 67
134 P006 21 22 P415 28
133 P007 23 24 P507 120
132 P008 25 26 P009 131
126 P012/VREFH 27 28 P013/VREFL 125
110 P801 29 30 P800 109
118 P505 31 32 P504 117
116 P503 33 34 P502 115
114 P501 35 36 VSS 122
121 VCC 37 38 P500 113
119 P506 39 40 P802 111
Color Key:
Secondary Fixed Function pins
4.6 Additional features
4.6.1 Analog reference voltages
A footprint for installation of capacitors C21 and C23 is provided on the Target
Board. These two capacitors provide noise-bypass capability for ports P010/P011
and for ports P012/P013. See Figure 21 for the circuit design.
Port pair P010/P011 may be assigned as GPIO, where bypass capacitor C21 would
damage signal quality. When P010/P011 are to be assigned as VREFH0/VREFL0,