RSK+RZA1H
8. Code Development
R20UT3007EG0200 Rev. 2.00
Page 47 of 53
May 17, 2015
8.5
Address Space
Figure 8.1 below details the address space of the MCU. This diagram is based on the Hardware Manual
version 1.0. For further details, refer to the RZ/A1H Group Hardware Manual.
1.
To enable SDRAM, JP18 must be open and SW6 #3 must be in the ON position (CS0_MBOOT2 low)
2.
To enable NOR FLASH, JP18 must be shorted and SW6 #3 must be in the ON position (CS0_MBBOOT2 low)
3.
To enable QSPI, JP18 must be shorted and SW6’s switches (SW6.1 – SW6.6) need to be set to: OFF, ON, OFF, ON, ON, ON.
4.
Note that SDRAM and NOR FLASH cannot be enabled at the same time.
5.
Device is 256MByte, but only 64MByte is addressable.
Figure 8.1: RZ/A1H Address Map On RSK
Board
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