RSK+RZA1H
5. User Circuitry
R20UT3007EG0200 Rev. 2.00
Page 20 of 53
May 17, 2015
5.10.1
QSPI Modes of Operation
There are several modes of operation of the QSPI memory in conjunction with the serial memory controller in
the RZ/A1H MCU. On the RSK+ board, there are two QSPI memory devices, attached to ports 0 and 1, of the
Multi I/O SPI controller’s channel 0. Channel 1 is used for other functions.
CS#
SCK
SI / IO0
SO / IO1
W# / IO2
HOLD# / IO3
CS#
SCK
SI / IO0
SO / IO1
W# / IO2
HOLD# / IO3
IC26 (Serial Flash 0)
IC25 (Serial Flash 1)
SPBSSL_0
SPBCLK_0
SPBMO0_0/SPBIO00
_0
SPBMI0_0/SPBIO10
_0
SPBIO20
_0
SPBIO30
_0
SPBMO1_0/SPBIO01_0
SPBMI1_0/SPBIO11_0
SPBIO21_0
SPBIO31_0
Channel 0
SPBSSL_1
SPBCLK_1
SPBMO0_1/SPBIO00
_1
SPBMI0_1/SPBIO10
_1
SPBMO1_1/SPBIO01_1
SPBMI1_1/SPBIO11_1
SPBIO21_1
SPBIO31_1
Channel 1
SPI multi I/O bus controller
PORT 0
PORT 1
SPBIO20_1
SPBIO30_1
PORT 0
PORT 1
Figure 5.1: RZ/A1H SPI multi I/O controller.
Each QSPI memory device can support one, two or four simultaneous serial lines of I/O. Furthermore, the
controller allows each channel’s ports to work in parallel, providing up to eight simultaneous serial lines of I/O
in dual QSPI mode. During the QSPI boot mode Port 0 is used and is accessed using only the clock,
SPBMO0 and SPBMI0 signals (Single bit Single channel).
T7
T6
T5
T4
T3
T2
T1
R1
R2
R3
R4
R5
R6
R7
T0
R0
SPBSSL
SPBCLK
SPBMO0
SPBMI0
Channel 0
Port 0
Serial
Flash
x
x
x
x
Figure 5.2: Single bit single channel operation mode.
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