RSK+RZA1H
5. User Circuitry
R20UT3007EG0200 Rev. 2.00
Page 21 of 53
May 17, 2015
It is important to recognise that these eight lines are serial inputs, and are not operating on the same byte, but
successive bytes. When operating over the two ports it should be noted that the memory structure is
fundamentally different from single channel operation, as lines 1-4 are working with the memory on Port 0 and
5-8 are working with Port 1. Figure 5.3 attempts to show this visually.
Serial Flash 0
PORT 0
PORT 1
NOT ACCESSED
Serial Flash 1
Byte1
Byte2
Byte3
Byte4
Byte5
Byte6
Byte7
Byte8
Byte9
Byte10
Byte11
Byte12
Byte13
Byte14
Byte15
Byte16
Byte1
Byte2
Byte3
Byte4
Byte5
Byte6
Byte7
Byte8
Byte9
Byte10
Byte11
Byte12
Byte13
Byte14
Byte15
Byte16
Serial Flash 0
PORT 0
PORT 1
Serial Flash 1
Byte1
Byte2
Byte3
Byte4
Byte5
Byte6
Byte7
Byte8
Byte9
Byte10
Byte11
Byte12
Byte13
Byte14
Byte15
Byte16
Byte1
Byte2
Byte3
Byte4
Byte5
Byte6
Byte7
Byte8
Byte9
Byte10
Byte11
Byte12
Byte13
Byte14
Byte15
Byte16
Dual Channel Mode
Single Channel Mode
Figure 5.3: Memory access of Single and Dual Mode QSPI Operation.
The consequence of this is that data stored in QSPI FLASH needs to be accessed in the same manner as it
has been programmed in. If data is accessed in Single QSPI mode when it has been programmed in Dual
QSPI mode, then every fourth group of four bytes will be missing. Conversely data accessed in Dual Channel
mode when it has been programmed in Single Channel mode will have blocks of four bytes from the other port
inserted between every fourth byte of correct data.
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