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RL78/I1D

Operation state switching IAR

R01AN3597EJ0100 Rev.1.00

Page 25 of 42

Jan. 31, 2017

4.7.9. The main user initialization

Figure 4.10 shows the flowchart of the main user initialization.

Figure 4.10

The main user initialization

4.7.10.

INTP0 interrupt enable processing

Figure 4.11 shows the flowchart of INTP0 interrupt enable processing.

Figure 4.11

INTP0 interrupt enable processing

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Summary of Contents for RL78/I1D

Page 1: ...n mode is switched one by one by the button pressing LV mode LS mode HS mode LS mode LP mode LS mode LV mode repetition at the following The power supply voltage VDD should be confirmed with the A D converter when switching to the HS mode and if the voltage is out of specified range the transition should be avoided Object device RL78 I1D When applying the application note to other microcomputers p...

Page 2: ...e main user initialization 25 4 7 10 INTP0 interrupt enable processing 25 4 7 11 12 bit interval timer start processing 26 4 7 12 Clock output start processing 26 4 7 13 Flash operation mode switching LV processing 27 4 7 14 Flash operation mode switching LS normal processing 29 4 7 15 Flash operation mode switching LS low consumption processing 31 4 7 16 Flash operation mode switching HS processi...

Page 3: ...e LV Low voltage main mode Regulator mode Normal setting Flash operation mode LS Low speed main mode Regulator mode Normal setting Flash operation mode LS Low speed main mode Regulator mode Low consumption setting Flash operation mode LS Low speed main mode Regulator mode Normal setting Flash operation mode HS High speed main mode Regulator mode Normal setting Flash operation mode LS Low speed mai...

Page 4: ...ntent MCU RL78 I1D R5F117GC Operating frequency High speed on chip oscillator HOCO clock 16 MHz 8MHz 4 MHz Middle speed on chip oscillator MOCO clock 4MHz 1MHz Low speed on chip oscillator clock 15KHz CPU peripheral hardware clock 16MHz 8MHz 4MHz 1 MHz Operation voltage 3 0 V operable at 1 6V 3 6V LVD operation VLVD LVD off Integrated development environment IAR Embedded Workbench for Renesas RL78...

Page 5: ...are structure Note It is the circuit image and shows the simplified outline of the connection Please design to do the pin processing etc appropriately and to meet with the electrical characteristics when the circuit is actually designed Please connect the input only port to VDD or VSS through a resistor individually 3 2 Used pin list Table 3 1 shows the used pin and function Table 3 1 Used pin and...

Page 6: ...ransition to the HS mode is not executed LED is blinked to inform the error Table 4 1 shows operation state detail and operation state transition Table 4 1 Operation state detail and operation state transition Transition state State LED1 LED2 Operation clock Range of operation voltage Status of the next transition 0 after reset LV mode Turning off Turning on HOCO 4MHz 1 6V 3 6V 1 1 LS mode Normal ...

Page 7: ...ram Table 4 3 Constants for the Sample Program Constant Setting Description _00_TRANSITION_STATUS_0 00H Transition status 0 _01_TRANSITION_STATUS_1 01H Transition status 1 _02_TRANSITION_STATUS_2 02H Transition status 2 _03_TRANSITION_STATUS_3 03H Transition status 3 _04_TRANSITION_STATUS_4 04H Transition status 4 _05_TRANSITION_STATUS_5 05H Transition status 5 _06_TRANSITION_STATUS_6 06H Transiti...

Page 8: ...ion uint16_t g_flash_mode State variable of flash operation mode r_it_interrupt switch_flashmode_to_LV switch_flashmode_to_LS_0 switch_flashmode_to_LS_1 switch_flashmode_to_HS switch_flashmode_to_LP uint16_t g_transition_status Transition state variable r_intc0_interrupt uint16_t g_ad_result Value of A D conversion result switch_flashmode_to_HS r_adc_interrupt uint16_t g_ad_busy A D conversion com...

Page 9: ... The flash operation state is switched to the LV mode switch_flashmode_to_LS_0 The flash operation state is switched to the LS normal mode switch_flashmode_to_LS_1 The flash operation state is switched to the LS low consumption mode switch_flashmode_to_HS The flash operation state is switched to the HS mode switch_flashmode_to_LP The flash operation state is switched to the LP mode switch_flashmod...

Page 10: ...ion After clearing the INTP0 interrupt request flag of it will allow the interrupt Parameter None Return value None R_IT_Start Outline 12 bit interval timer start processing Header r_cg_macrodriver h r_cg_userdefine h r_cg_it h Declaration void R_IT_Start void Explanation Start the count operation of the 12 bit interval timer Parameter None Return value None R_PCLBUZ1_Start Outline Clock output st...

Page 11: ...shmode_to_LS_0 Outline The flash operation state is switched to LS normal mode Header r_cg_intc h Declaration void switch_flashmode_to_LS_0 void Explanation The flash operation state is switched to LS normal mode Parameter None Return value None switch_flashmode_to_LS_1 Outline The flash operation state is switched to LS low consumption mode Header r_cg_intc h Declaration void switch_flashmode_to_...

Page 12: ... value None r_adc_interrupt Outline A D conversion complete interrupt processing Header r_cg_macrodriver h r_cg_userdefine h r_cg_adc h Declaration __interrupt static void r_adc_interrupt void Explanation A D function is stopped and the result of A D conversion is stored in RAM area Parameter None Return value None R_ADC_Result Outline A D conversion result acquisition process Header r_cg_macrodri...

Page 13: ...t_interrupt Outline 12 bit interval timer interrupt processing Header r_cg_macrodriver h r_cg_userdefine h r_cg_intc h r_cg_intp h Declaration __interrupt static void r_it_interrupt void Explanation LED state is updated according to the state of operation state Parameter None Return value None ...

Page 14: ... Figure 4 1 shows the whole flowchart Figure 4 1 Overall Flow 4 7 1 The main processing Figure 4 2 shows the flowchart of main processing main while 1 loop Main initialization functionR_MAIN_UserInit HALT external interrupt input INTP0 Initialization setting function hdwinit Figure 4 2 The main processing ...

Page 15: ... 4 3 shows the flowchart of initialization flow chart hdwinit Maskable interrupt disable Peripheral function initialization R_Systeminit return IE 0 Port initialization CPU clock initialization 12 bit interval timer initialization Clock output initialization External interrupt initialization Figure 4 3 Initialization ...

Page 16: ...of peripheral function initialization Figure 4 4 Peripheral function initialization 4 7 4 I O Port Setup Figure 4 5 shows the flowchart of I O Port Setup Figure 4 5 I O Port Setup Caution Provide proper treatment for unused pins so that their electrical specifications are observed Connect each of any unused input only ports to VDD or VSS via a separate resistor ...

Page 17: ...0 0 0 1 1 Bit 1 P61 P61 I O mode selection 0 Output 0 1 Output 1 Bit 0 P60 P60 I O mode selection 0 Output 0 1 Output 1 Symbol PM6 7 6 5 4 3 2 1 0 1 1 1 1 PM63 PM62 PM61 PM60 1 1 1 1 0 0 0 0 Bit 1 PM61 PM61 I O mode selection 0 Output mode output buffer on 1 Input mode output buffer off Bit 0 PM60 PM60 I O mode selection 0 Output mode output buffer on 1 Input mode output buffer off Caution For det...

Page 18: ...0100 Rev 1 00 Page 18 of 42 Jan 31 2017 4 7 5 CPU clock initialization Figure 4 6 shows the flowchart of CPU clock initialization Figure 4 6 CPU clock initialization Note Refer to RL78 G13 R01AN2575J application note for CPU clock setting R_CGC_Create ...

Page 19: ...ternal clock input mode Input port External clock input Bits 5 and 4 EXCLKS OSCSELS Subsystem clock pin operation mode XT1 P123 pin XT2 EXCLKS P124 pin 0 0 Input port mode Input port 0 1 XT1 oscillation mode Crystal resonator connection 1 0 Input port mode Input port 1 1 External clock input mode Input port External clock input Caution For details on the register setup procedures refer to RL78 I1D...

Page 20: ...rnal clock from EXCLK pin is valid Input port 1 X1 oscillator stopped External clock from EXCLK pin is invalid Bit 6 XTSTOP Subsystem clock operation control X1 oscillation mode External clock input mode Input port mode 0 X1 oscillator operating External clock from EXCLKS pin is valid Input port 1 XT1 oscillator stopped External clock from EXCLKS pin is invalid Bit 1 MIOEN High speed on chip oscil...

Page 21: ...bit interval timer Low speed on chip oscillator clock Controlling the operation speed mode Symbol OSMC 7 6 5 4 3 2 1 0 RTCLPC 0 0 WUTMM CK0 0 0 0 0 0 0 0 1 0 0 0 0 Bit 7 RTCLPC Setting in STOP mode or HALT mode while subsystem clock is selected as CPU clock 0 Enables supply of subsystem clock to peripheral functions 1 Stops supply of subsystem clock to peripheral functions other than real time clo...

Page 22: ...on of CPU peripheral hardware clock fCLK 0 Main system clock fMAIN 1 Subsystem clock fSUB Bit 4 MCM0 Main system clock fMAIN operation control 0 Selects the high speed on chip oscillator clock fIH as the main system clock fMAIN 1 Selects the high speed system clock fMX as the main system clock fMAIN Bit 0 MCM1 Main system clock fMAIN operation control 0 High speed on chip oscillator clock 1 Middle...

Page 23: ...rupt request flag clear return 12 bit interval timer Interrupt disable ITMC register 05DBH MK1H register TMKAMK bit 1 INTIT interrupt disable 12 bit interval timer interrupt priority level setting PR11L register TMKAPR1 bit 1 PR01L register TMKAPR1 bit 1 INTIT interrupt priority level 3 lowest 12 bit interval timer count operation stop 12 bit interval timer Set interrupt period to 100ms 12 bit int...

Page 24: ... clock output initialization 4 7 8 INTP0 initialization Figure 4 9 shows the flowchart of INTP0 initialization R_INTP0_Create return INTPn interrupt disabled Clear INTPn interrupt request flag PMK6 PMK0 bit 1 PIF6 PIF0 bit 0 INTP0 valid edge setting Enable the falling edge INTP0 interrupt priority Set to level 3 lowest PPR10 bit 1 PPR00 bit 1 EGN0 bit 1 EGP0 bit 0 Figure 4 9 INTP0 initialization ...

Page 25: ...7 9 The main user initialization Figure 4 10 shows the flowchart of the main user initialization Figure 4 10 The main user initialization 4 7 10 INTP0 interrupt enable processing Figure 4 11 shows the flowchart of INTP0 interrupt enable processing Figure 4 11 INTP0 interrupt enable processing ...

Page 26: ...it interval timer start processing Figure 4 12 shows the flowchart of 12 bit interval timer start processing Figure 4 12 12 bit interval timer start processing 4 7 12 Clock output start processing Figure 4 13 shows the flowchart of clock output start processing Figure 4 13 Clock output start processing ...

Page 27: ... R01AN3597EJ0100 Rev 1 00 Page 27 of 42 Jan 31 2017 4 7 13 Flash operation mode switching LV processing Figure 4 14 shows the flowchart of the flash operation mode switching LV processing Figure 4 14 Flash operation switching LV processing ...

Page 28: ...tting Regulator mode control Symbol FLMWRP 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 FLMWEN 0 0 0 0 0 0 0 1 Bit 0 FLMWEN Control of regulator mode 0 Rewriting the FLMODE register is disabled 1 Rewriting the FLMODE register is enabled Caution For details on the register setup procedures refer to RL78 I1D User s Manual Hardware Flash operating mode protect register FLMWRP Control of the flash operation mode sel...

Page 29: ...0 Rev 1 00 Page 29 of 42 Jan 31 2017 4 7 14 Flash operation mode switching LS normal processing Figure 4 15 Figure 4 16 shows the flowchart of the flash operation mode switching LS normal Figure 4 15 Flash operation mode switching LS normal processing 1 2 ...

Page 30: ...RL78 I1D Operation state switching IAR R01AN3597EJ0100 Rev 1 00 Page 30 of 42 Jan 31 2017 Figure 4 16 Flash operation mode switching LS normal processing 2 2 ...

Page 31: ...chip oscillator clock MCM1 bit 1 Select middle speed on chip oscillator clock MCS1 1 Yes No Set the high speed on chip oscillator to stop HIOSTOP bit 1 High speed on chip oscillator stop Set flash operation mode to LS low speed main mode FLMWEN bit 1 Rewriting the FLMODE register is enabled FLMODE register 80H LS low speed main mode FLMWEN bit 0 Rewriting the FLMODE register is disabled Updated st...

Page 32: ...ck status in the case of middle speed on chip oscillator clock switch to the high speed on chip oscillator clock Set the high speed on chip oscillator clock to the main on chip oscillator clock MCM1 bit 0 Select high speed on chip oscillator clock MCS1 0 Yes No Set the middle speed on chip oscillator to stop MIOEN bit 0 Middle speed on chip oscillator stop Wait until the status of the main on chip...

Page 33: ... g_flash_mode _10_FLAHMODE_HS_ERROR Updated status flag variable of flash operation mode g_flash_mode _04_FLAHMODE_HS Set flash operation mode to HS high speed main mode FLMWEN bit 1 Rewriting the FLMODE register is enabled FLMODE register C0H HS high speed main mode FLMWEN bit 0 Rewriting the FLMODE register is disabled Updated status flag variable of flash operation mode Set the high speed on ch...

Page 34: ... 00001B ADISS bit 1 ADM2 register 00H ADTYP 0 12 bit resolution ADREFP1 ADREF0 bits 00B Provide from AVDD ADREFM 0 Provide from AVSS A D converter clock provision PER0 register ADCEN bit 1 Start input clock provision A D converter circuit operation stop A D converter initialization Set conversion time about 76us Set select mode Set software trigger mode Set one shot conversion mode Reference volta...

Page 35: ...D conversion operation start processing Figure 4 21 shows the flowchart of A D converter initialization Figure 4 21 A D conversion operation start processing 4 7 19 A D converter stop processing Figure 4 22 shows the flowchart of A D converter initialization Figure 4 22 A D converter stop processing ...

Page 36: ...r clock to the main on chip oscillator clock MCM1 bit 1 Select middle speed on chip oscillator clock MCS1 1 Yes No Set the high speed on chip oscillator to stop HIOSTOP bit 1 High speed on chip oscillator stop Wait until the status of the main on chip oscillator clock is switched to the middle speed on chip oscillator clock Set the regulator mode to the normal setting PMMC register MCSEL bit 0 g_f...

Page 37: ... R01AN3597EJ0100 Rev 1 00 Page 37 of 42 Jan 31 2017 4 7 21 External interruption INTP0 processing Figure 4 24 Figure 4 25 shows the flowchart of the external interruption INTP0 processing Figure 4 24 External interrupt INTP0 processing 1 2 ...

Page 38: ...RL78 I1D Operation state switching IAR R01AN3597EJ0100 Rev 1 00 Page 38 of 42 Jan 31 2017 Figure 4 25 External interrupt INTP0 processing 2 2 ...

Page 39: ... Turning off P6 0 LED0 Turning on P6 1 LED1 Turning on P6 0 LED0 Blinking low speed P6 1 LED1 Turning off P6 0 LED0 Blinking super high speed P6 1 LED1 Blinking super high speed _00_FLASHMODE_LV LV mode _01_FLASHMODE_LS_0 LS normal mode _02_FLASHMODE_LS_1 LS low consumption mode _04_FLASHMODE_HS HS mode _08_FLASHMODE_LP LP mode _10_FLASHMODE_HS_ERROR HS error mode Blinking low speed Off On or On O...

Page 40: ...essing Figure 4 27 shows the flowchart of the A D conversion complete interrupt processing Figure 4 27 A D conversion complete interrupt processing 4 7 24 A D conversion result acquisition process Figure 4 28 shows the flowchart of the A D conversion result acquisition processing Figure 4 28 A D conversion result acquisition processing ...

Page 41: ...ly current measurement mode Table 5 1 Details and transition of power supply current measurement mode Transition state State Operation clock Range of operation voltage Status of the next transition 0 after reset LV mode HOCO 4MHz 1 6V 3 6V 1 1 LV mode MOCO 4MHz 1 8V 3 6V 2 2 LS mode low consumption setting MOCO 4MHz 1 8V 3 6V 3 3 LS mode Normal setting HOCO 8MHz 1 8V 3 6V 4 or 4 Error 4 HS mode HO...

Page 42: ...Hardware R01UH0474E RL78 family user s manual software R01US0015E Please get the latest version from Renesas Electronics homepage Technical update Please acquire latest information from Renesas Electronics homepage Website and support Renesas Electronics Website http japan renesas com Inquiries http japan renesas com contact All trademarks and registered trademarks are the property of their respec...

Page 43: ...A 1 modification record RL78 I1D Operation state switching IAR Rev Date Revision Page Summary 1 00 Jan 31 2017 First Edition ...

Page 44: ...ip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guara...

Page 45: ...ention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or systems manufactured by you 8 Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics pr...

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