RL78/I1D
Operation state switching IAR
R01AN3597EJ0100 Rev.1.00
Page 23 of 42
Jan. 31, 2017
4.7.6. 12-bit interval timer initialization
Figure 4.7 shows the flowchart of 12-bit interval timer initialization.
R_IT_Create
12-bit interval timer
clock provision
PER2 register
TMKAEN bit
1
ITMC register
0000H
RINTE bit = 0 : Count operation stop ( count clear)
IF1H register
TMKAIF bit
0
: INTIT interrupt request flag clear
return
12-bit interval timer
Interrupt disable
ITMC register
05DBH
MK1H register
TMKAMK bit
1 : INTIT interrupt disable
12-bit interval timer
interrupt priority level setting
PR11L register
TMKAPR1 bit
1
PR01L register
TMKAPR1 bit
1 : INTIT interrupt priority level 3 (lowest)
12-bit interval timer count operation
stop
12-bit interval timer
Set interrupt period to 100ms
12-bit interval timer
reset control
PRR2 register
TMKARES bit
1 :12-bit interval timer reset state
TMKARES bit
0 :12-bit interval timer reset release
Figure 4.7
12-bit interval timer initialization