RL78/I1D
Operation state switching IAR
R01AN3597EJ0100 Rev.1.00
Page 21 of 42
Jan. 31, 2017
Subsystem clock select register (CKSEL)
Select the sub clock or low-speed on-chip oscillator clock
: low-speed on-chip oscillator clock
Subsystem clock select
Symbol: CKSEL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
SELLOSC
0
0
0
0
0
0
0
1
Bit 0
SELLOSC
Selection of sub clock/low-speed on-chip oscillator clock
0
Sub clock
1
Low-speed on-chip oscillator clock
Operation speed mode control register (OSMC)
Setting in STOP mode or HALT mode while subsystem clock is selected as CPU clock
: Enable supply of subsystem clock to peripheral functions.
Operating clock for the real-time clock and 12-bit interval timer
: Low-speed on-chip oscillator clock
Controlling the operation speed mode
Symbol: OSMC
7
6
5
4
3
2
1
0
RTCLPC
0
0
WUTMM
CK0
0
0
0
0
0
0
0
1
0
0
0
0
Bit 7
RTCLPC
Setting in STOP mode or HALT mode while subsystem clock is selected as CPU
clock
0
Enables supply of subsystem clock to peripheral functions
1
Stops supply of subsystem clock to peripheral functions other than real-time clock
and 12-bit interval timer
Bit 4
WUTMMCK
0
Selection of operation clock for real-time clock and 12-bit interval timer
0
Subsystem clock
1
Low-speed on-chip oscillator clock
Caution: The OSMC register is intended to be used to reduce power consumption by reducing the
operating current of the device in the STOP and HALT modes while the subsystem clock is
selected as CPU clock. For details on the register setup procedures, refer to RL78/I1D User's
Manual: Hardware.
