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M32R-FPU Software Manual (Rev.1.01)

INSTRUCTIONS

3.2 Instruction description

[Supplemental Operation Description]

The following shows the values of Rsrc1 and Rsrc2 and the operation results when DN = 0 and

DN = 1.

DN = 0

Rsrc2

add

UIPL

QNaN

SNaN

QNaN

SNaN

(Note)

+Infinity

IVLD

-Infinity

-0

+Infinity

-Infinity

Denormalized

Number

Denormalized

Number

Normalized

Number

Normalized

Number

-0

Rsrc1

Rsrc2

add

QNaN

SNaN

QNaN

SNaN

(Note)

+Infinity

IVLD

-Infinity

-0

+Infinity

-Infinity

Rsrc1

Normalized Number

Normalized

Number

Normalized

Number

Normalized

Number

+0, +

-0, -

Denormalized

Number

+0, +

Denormalized

Number

Denormalized

Number

Denormalized

Number

DN = 1

IVLD: Invalid Operation Exception

UIPL: Unimplemented Exception

NaN: Not a Number

SNaN: Signaling NaN

QNaN: Quiet NaN

Note: The rounding mode is “-0” when rounding toward “-Infinity”, and “+0” when rounding

toward any other direction.

FADD

floating point Instructions

Floating-point addd

[M32R-FPU Extended Instruction]

Summary of Contents for M32R-FPU

Page 1: ...ok over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electron...

Page 2: ...t for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas...

Page 3: ...roducts and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest informa...

Page 4: ...here may contain technical inaccuracies or typographical errors Renesas Technology Corporation assumes no responsibility for any damage liability or other loss rising from these inaccuracies or error...

Page 5: ...ted BTST instruction APPENDICES 3 Appendix Figure 3 1 1 corrected Incorrect The E1 stage of the FDIV instruction requires 13 cycles Correct The E1 stage of the FDIV instruction requires 14 cycles Appe...

Page 6: ...nt Status Register FPSR CR7 1 6 1 3 6 Floating Point Exceptions FPE 1 8 1 4 Accumulator 1 11 1 5 Program counter 1 11 1 6 Data format 1 12 1 6 1 Data type 1 12 1 6 2 Data format 1 13 1 7 Addressing mo...

Page 7: ...ppendix 5 IEEE754 Specification Overview Appendix 18 Appendix 5 1 Floating Point Formats Appendix 18 Appendix 5 2 Rounding Appendix 20 Appendix 5 3 Exceptions Appendix 20 Appendix 6 M32R FPU Specifica...

Page 8: ...M32R FPU Software Manual Rev 1 01 This page left blank intentionally...

Page 9: ...CHAPTER 1 CPU PROGRAMMIING MODEL 1 1 CPU Register 1 2 General purpose Registers 1 3 Control Registers 1 4 Accumulator 1 5 Program Counter 1 6 Data Format 1 7 Addressing Mode...

Page 10: ...r calculations floating point operations etc R14 is used as the link register and R15 as the stack pointer The link register is used to store the return address when executing a subroutine call instru...

Page 11: ...these control registers In addition the SM bit IE bit and C bit of the PSW can also be set by the SETPSW instruction or the CLRPSW instruction Figure 1 3 1 Control Registers Backup PC Floating point...

Page 12: ...b0 0 0 0 0 0 0 0 0 0 0 0 0 0 BC SM IE C 23 24 25 26 27 28 29 30 b31 17 18 19 20 21 22 b16 BIE BSM BPSW field 0 0 PSW field At reset release B 0000 0000 0000 0000 00 000 0000 0000 b Bit Name Function...

Page 13: ...he address of the current stack pointer These registers can be accessed as the general purpose register R15 R15 switches between representing the SPI and SPU depending on the value of the Stack Mode S...

Page 14: ...FV Set to 1 when an invalid operation exception R W Invalid Operation Exception occurs if EIT processing is unexecuted Note 1 Flag Once set the flag retains the value 1 until it is cleared to 0 in so...

Page 15: ...3 Zero Divide Exception 1 A zero divide exception occurred Cause Bit When the bit is set to 1 the execution of an FPU operation instruction will clear it to 0 28 CO 0 No overflow exception occurred R...

Page 16: ...finity MAX infinity infinity infinity MAX No change 0 MAX MAX Nearest infinity infinity Note 1 When the Overflow Exception Enable EO bit FPSR register bit 20 0 Note 2 When the Overflow Exception Enabl...

Page 17: ...register bit 17 0 Note 2 When the Inexact Exception Enable EX bit FPSR register bit 17 1 4 Zero Division Exception DIV0 The exception occurs when a finite nonzero value is divided by zero The followin...

Page 18: ...ister bit 21 0 Note 2 When the Invalid Operation Exception Enable EV bit FPSR register bit 21 1 Notes NaN Not a Number SNaN Signaling NaN a NaN in which the MSB of the decimal fraction is 0 When SNaN...

Page 19: ...32 63 respectively Use the MVFACHI MVFACLO and MVFACMI instructions for reading data from the accumulator The MVFACHI MVFACLO and MVFACMI instructions read data from the high order 32 bits bits 0 31 t...

Page 20: ...e signed integers are represented by 2 s complements CPU PROGRAMMING MODEL 1 6 Data Format b7 b0 signed byte 8 bit integer unsigned byte 8 bit integer signed halfword 16 bit integer b0 b0 b0 b0 b0 b7...

Page 21: ...6 bit data on the LSB side and the 8 bit data on the LSB side of the register are stored into memory by the ST STH and STB instructions respectively Rn b0 b31 load byte Rn b0 b31 halfword Rn b0 b31 wo...

Page 22: ...ligned with a halfword boundary least significant address bit 0 or a word boundary two low order address bits 00 respectively If an attempt is made to access memory data that overlaps the halfword or...

Page 23: ...he register contents Can only be specified with LD instruction Add 2 to register contents R M32R FPU extended addressing mode The contents of the register specify the memory address then 2 is added to...

Page 24: ...1 1 16 M32R FPU Software Manual Rev 1 01 CPU PROGRAMMING MODEL 1 7 Addressing Mode This page left blank intentionally...

Page 25: ...CHAPTER 2 INSTRUCTION SET 2 1 Instruction set overview 2 2 Instruction format...

Page 26: ...structions M32R CPU supports compound instructions such as load address update and store address update which are useful for high speed data transfer 2 1 1 Load store instructions The load store instr...

Page 27: ...egister specify the memory address then 2 is added to the register contents Can only be specified with STH instruction Add 4 to register contents R The contents of the register is added by 4 the regis...

Page 28: ...ation instructions Compare arithmetic logic operation multiply and divide and shift are carried out between registers compare instructions CMP Compare CMPI Compare immediate CMPU Compare unsigned CMPU...

Page 29: ...VU Divide unsigned MUL Multiply REM Remainder REMU Remainder unsigned shift instructions SLL Shift left logical SLL3 Shift left logical 3 operand SLLI Shift left logical immediate SRA Shift right arit...

Page 30: ...ater than or equal to zero BGTZ Branch on greater than zero BL Branch and link BLEZ Branch on less than or equal to zero BLTZ Branch on less than zero BNC Branch on not C bit BNE Branch on not equal t...

Page 31: ...ample refer to Figure 2 1 1 When instruction A or B is a branch instruction branching to instruction G the immediate value of either instruction A or B becomes 4 Simultaneous with execution of branchi...

Page 32: ...ator and a general purpose register MACHI Multiply accumulate high order halfwords MACLO Multiply accumulate low order halfwords MACWHI Multiply accumulate word and high order halfword MACWLO Multiply...

Page 33: ...ction MULWHI instruction Rsrc2 32 bits Rsrc1 0 15 16 31 H L 0 15 16 31 H L x x MACLO instruction MACHI instruction Rsrc2 ACC 0 63 0 63 Rsrc1 0 31 32 bits 0 15 16 31 H L x x MACWLO instruction MACWHI i...

Page 34: ...essed in two steps Refer to Chapter 3 for details Fig 2 1 4 DSP function instruction operation 3 transfer between accumulator and register Rdest 0 31 ACC 0 63 15 16 31 32 47 48 MVFACHI instruction Rsr...

Page 35: ...ing point divede FMADD Floating point multiply and add FMSUB Floating point multiply and subtract ITOF Integer to float UTOF Unsigned integer to float FTOI Float to integer FTOS Float to short FCMP Fl...

Page 36: ...uction and 32 bit instruction 16 bit instruction op1 R1 R2 op2 op1 R1 c op1 cond c op1 R1 R2 op2 c op1 R1 R2 op2 c op1 R1 c op1 cond c 32 bit instruction R1 R1 op R2 R1 R1 op c Branch Short Displaceme...

Page 37: ...ction as instruction B for parallel execution The MSB of the NOP instruction used for word arraignment adjustment is changed to 1 automatically by a standard Mitsubishi assembler then the M32R FPU can...

Page 38: ...2 2 14 M32R FPU Software Manual Rev 1 01 This page left blank intentionally INSTRUCTION SET 2 2 Instruction format...

Page 39: ...CHAPTER 3 INSTRUCTIONS 3 1 Conventions for instruction description 3 2 Instruction description...

Page 40: ...ecify the memory address R register indirect and Subtract 4 to register contents 4 is subtract to the register register update contents hen the register contents specify the memory address imm immedia...

Page 41: ...logical operator OR logical operator NOT logical operator execute a conditional expression conditional operator Table 3 1 4 Operation expression bit operator operator meaning bits are left shifted bi...

Page 42: ...eption FPE and trap TRAP may result from an instruction execution Instruction format Shows the bit level instruction pattern 16 bits or 32 bits Source and or destination register numbers are put in th...

Page 43: ...rc Add Rdest Rdest Rsrc None Add Rde 0000 dest 1010 src instruction function expression corresponds to C language method instruction description and effect on condition bit C EIT events which may occu...

Page 44: ...c ADD 1010 arithmetic logic operation Add src Mnemonic ADD Rdest Rsrc Function Add Rdest Rdest Rsrc Description ADD adds Rsrc to Rdest and puts the result in Rdest The condition bit C is unchanged EIT...

Page 45: ...ds the 16 bit immediate value to Rsrc and puts the result in Rdest The immediate value is sign extended to 32 bits before the operation The condition bit C is unchanged EIT occurrence None Encoding AD...

Page 46: ...DI adds the 8 bit immediate value to Rdest and puts the result in Rdest The immediate value is sign extended to 32 bits before the operation The condition bit C is unchanged EIT occurrence None Encodi...

Page 47: ...0 Description ADDV adds Rsrc to Rdest and puts the result in Rdest The condition bit C is set when the addition results in overflow otherwise it is cleared EIT occurrence None Encoding ADDV dest 0000...

Page 48: ...ue to Rsrc and puts the result in Rdest The immediate value is sign extended to 32 bits before it is added to Rsrc The condition bit C is set when the addition results in overflow otherwise it is clea...

Page 49: ...on ADDX adds Rsrc and C to Rdest and puts the result in Rdest The condition bit C is set when the addition result cannot be represented by a 32 bit unsigned integer otherwise it is cleared EIT occurre...

Page 50: ...tion AND src dest Mnemonic AND Rdest Rsrc Function Logical AND Rdest Rdest Rsrc Description AND computes the logical AND of the corresponding bits of Rdest and Rsrc and puts the result in Rdest The co...

Page 51: ...omputes the logical AND of the corresponding bits of Rsrc and the 16 bit immediate value which is zero extended to 32 bits and puts the result in Rdest The condition bit C is unchanged EIT occurrence...

Page 52: ...gned x 8 8 Description BC causes a branch to the specified label when the condition bit C is 1 There are two instruction formats which allows software such as an assembler to decide on the better form...

Page 53: ...he displacement is sign extended before the address calculation bitpos becomes 0 to 7 MSB becomes 0 and LSB becomes 7 The memory is accessed in bytes The LOCK bit is on while the BCLR instruction is e...

Page 54: ...p16 Function Branch if Rsrc1 Rsrc2 PC PC 0xfffffffc signed short pcdisp16 2 Description BEQ causes a branch to the specified label when Rsrc1 is equal to Rsrc2 The condition bit C is unchanged EIT occ...

Page 55: ...c pcdisp16 Function Branch if Rsrc 0 PC PC 0xfffffffc signed short pcdisp16 2 Description BEQZ causes a branch to the specified label when Rsrc is equal to zero The condition bit C is unchanged EIT oc...

Page 56: ...Branch if signed Rsrc 0 PC PC 0xfffffffc signed short pcdisp16 2 Description BGEZ causes a branch to the specified label when Rsrc treated as a signed 32 bit value is greater than or equal to zero The...

Page 57: ...Branch if signed Rsrc 0 PC PC 0xfffffffc signed short pcdisp16 2 Description BGTZ causes a branch to the specified label when Rsrc treated as a signed 32 bit value is greater than zero The condition b...

Page 58: ...c sign_extend pcdisp24 2 where define sign_extend x signed x 8 8 Description BL causes an unconditional branch to the address specified by the label and puts the return address in R14 There are two in...

Page 59: ...f signed Rsrc 0 PC PC 0xfffffffc signed short pcdisp16 2 Description BLEZ causes a branch to the specified label when the contents of Rsrc treated as a signed 32 bit value is less than or equal to zer...

Page 60: ...Branch if signed Rsrc 0 PC PC 0xfffffffc signed short pcdisp16 2 Description BLTZ causes a branch to the specified label when Rsrc treated as a signed 32 bit value is less than zero The condition bit...

Page 61: ...c sign_extend pcdisp24 2 where define sign_extend x signed x 8 8 Description BNC branches to the specified label when the condition bit C is 0 There are two instruction formats this allows software su...

Page 62: ...p16 Function Branch if Rsrc1 Rsrc2 PC PC 0xfffffffc signed short pcdisp16 2 Description BNE causes a branch to the specified label when Rsrc1 is not equal to Rsrc2 The condition bit C is unchanged EIT...

Page 63: ...c pcdisp16 Function Branch if Rsrc 0 PC PC 0xfffffffc signed short pcdisp16 2 Description BNEZ causes a branch to the specified label when Rsrc is not equal to zero The condition bit C is unchanged EI...

Page 64: ...isp24 2 where define sign_extend x signed x 8 8 Description BRA causes an unconditional branch to the address specified by the label There are two instruction formats this allows software such as an a...

Page 65: ...to 1 The displacement is sign extended before the address calculation bitpos becomes 0 to 7 MSB becomes 0 and LSB becomes 7 The memory is accessed in bytes The LOCK bit is on while the BSET instructio...

Page 66: ...Instruction Mnemonic BTST bitpos Rsrc Function Remove the bit specified by the register C Rsrc 7 bitpos 1 Description Take out the bit specified as bitpos within the Rsrc lower eight bits and sets it...

Page 67: ...tion Set the undefined SM IE and C bits of PSW to 0 PSW imm8 0xffffff00 Description Set the AND result s of the reverse value of b0 MSB b1 and b7 LSB of the 8 bit immediate value and bits SM IE and C...

Page 68: ...igned Rsrc1 signed Rsrc2 1 0 Description The condition bit C is set to 1 when Rsrc1 is less than Rsrc2 The operands are treated as signed 32 bit values EIT occurrence None Encoding src1 0000 CMP Rsrc1...

Page 69: ...condition bit C is set when Rsrc is less than 16 bit immediate value The operands are treated as signed 32 bit values The immediate value is sign extended to 32 bit before the opera tion EIT occurrenc...

Page 70: ...ed Rsrc1 unsigned Rsrc2 1 0 Description The condition bit C is set when Rsrc1 is less than Rsrc2 The operands are treated as un signed 32 bit values EIT occurrence None Encoding src1 0000 CMPU Rsrc1 R...

Page 71: ...ondition bit C is set when Rsrc is less than the 16 bit immediate value The operands are treated as unsigned 32 bit values The immediate value is sign extended to 32 bit before the operation EIT occur...

Page 72: ...d Rdest signed Rsrc Description DIV divides Rdest by Rsrc and puts the quotient in Rdest The operands are treated as signed 32 bit values and the result is rounded toward zero The condition bit C is u...

Page 73: ...c and puts the quotient in Rdest The operands are treated as unsigned 32 bit values and the result is rounded toward zero The condition bit C is unchanged When Rsrc is zero Rdest is unchanged EIT occu...

Page 74: ...est The result is rounded according to the RM field of FPSR The DN bit of FPSR handles the modification of denormalized numbers The condition bit C remains unchanged EIT occurrence Floating Point Exce...

Page 75: ...ed Number 0 Rsrc1 Rsrc2 add QNaN QNaN SNaN QNaN SNaN 0 Note Note Infinity Infinity IVLD IVLD IVLD Infinity Infinity Infinity Infinity 0 Infinity Infinity Rsrc1 Normalized Number Normalized Number Norm...

Page 76: ...st The results of the comparison can be determined y the following methods The DN bit of FPSR handles the conversion of denormalized numbers The condition bit C remains unchanged EIT occurrence Floati...

Page 77: ...ty IVLD comparison invalid Infinity Infinity 00000000 00000000 00000000 0 Infinity Infinity Infinity Infinity 0 Rsrc1 Normalized Number Normalized Number comparison Denormalized Number Denormalized Nu...

Page 78: ...can be determined y the following methods Note Only when EV bit b21 of FPSR Register 0 The DN bit of FPSR handles the conversion of denormalized numbers The condition bit C remains unchanged EIT occur...

Page 79: ...finity IVLD Infinity Infinity 00000000 00000000 00000000 0 Infinity Infinity Infinity Infinity 0 Rsrc1 Normalized Number Normalized Number Denormalized Number Denormalized Number comparison Rsrc2 QNaN...

Page 80: ...result in Rdest The result is rounded according to the RM field of FPSR The DN bit of FPSR handles the modification of denormalized numbers The condition bit C remains unchanged EIT occurrence Floati...

Page 81: ...SNaN QNaN SNaN 0 0 0 0 0 0 Infinity Infinity Infinity IVLD DIV0 IVLD IVLD Infinity Infinity Infinity Infinity 0 0 0 Infinity Infinity 0 Rsrc1 Normalized Number Normalized Number Denormalized Number D...

Page 82: ...Add the result of Step 1 the rounded value and the floating point single precision value stored in Rdest The result is rounded according to the RM field of FPSR The result of this operation is stored...

Page 83: ...d Infinity and 0 when rounding toward any other direction Rsrc2 Multiplication UIPL QNaN QNaN SNaN QNaN SNaN 0 0 0 0 Infinity Infinity Infinity IVLD Infinity Infinity IVLD IVLD Infinity Infinity Infin...

Page 84: ...N SNaN QNaN SNaN 0 0 0 0 0 0 Infinity Infinity Infinity IVLD Infinity Infinity IVLD IVLD Infinity Infinity Infinity 0 0 Infinity Infinity Normalized Number Normalized Number Multiplication Denormalize...

Page 85: ...t the result rounded value of Step 1 from the floating point single precision value stored in Rdest The subtraction result is rounded according to the RM field of FPSR The result of this operation is...

Page 86: ...inity and 0 when rounding toward any other direction Rsrc2 Multiplication UIPL QNaN QNaN SNaN QNaN SNaN 0 0 0 0 Infinity Infinity Infinity IVLD Infinity Infinity IVLD IVLD Infinity Infinity Infinity 0...

Page 87: ...N SNaN QNaN SNaN 0 0 0 0 0 0 Infinity Infinity Infinity IVLD Infinity Infinity IVLD IVLD Infinity Infinity Infinity 0 0 Infinity Infinity Normalized Number Normalized Number Multiplication Denormalize...

Page 88: ...and store the results in Rdest The result is rounded according to the RM field of FPSR The DN bit of FPSR handles the modification of denormalized numbers The condition bit C remains unchanged EIT oc...

Page 89: ...0 0 0 0 Infinity Infinity Infinity IVLD Infinity Infinity IVLD IVLD Infinity Infinity Infinity 0 0 0 Infinity Infinity 0 Rsrc1 Normalized Number Normalized Number Denormalized Number Denormalized Num...

Page 90: ...1 and store the results in Rdest The result is rounded according to the RM field of FPSR The DN bit of FPSR handles the modification of denormalized numbers The condition bit C remains unchanged EIT o...

Page 91: ...y Infinity 0 Infinity Infinity Rsrc1 Normalized Number Normalized Number Subtraction 0 0 Denormalized Number Denormalized Number 0 0 Denormalized Number Denormalized Number Supplemental Operation Desc...

Page 92: ...on value stored in Rsrc to a 32 bit integer and store the result in Rdest The result is rounded toward 0 regardless of the value in the RM field of FPSR The condition bit C remains unchanged EIT occur...

Page 93: ...igned bit 0 H 7FFF FFFF Signed bit 1 H 8000 0000 Note 1 Inexact Exception occurs when rounding is performed 2 Inexact Exception does not occur when Rsrc H CF00 0000 DN 1 Rsrc Value exponent with no bi...

Page 94: ...ion value stored in Rsrc to a 16 bit integer and store the result in Rdest The result is rounded toward 0 regardless of the value in the RM field of FPSR The condition bit C remains unchanged EIT occu...

Page 95: ...0 H 0000 7FFF Signed bit 1 H FFFF 8000 Note 1 Inexact Exception occurs when rounding is performed 2 Inexact Exception does not occur when Rsrc H CF00 0000 DN 1 Rsrc Value exponent with no bias Rdest...

Page 96: ...ored in Rsrc to a floating point single precision value and stores the result in Rdest The result is rounded according to the RM field of FPSR The condition bit C remains unchanged H 0000 0000 is hand...

Page 97: ...routine call register direct R14 PC 0xfffffffc 4 PC Rsrc 0xfffffffc Description JL causes an unconditional jump to the address specified by Rsrc and puts the return address in R14 The condition bit C...

Page 98: ...n Jump Mnemonic JMP Rsrc Function Jump PC Rsrc 0xfffffffc Description JMP causes an unconditional jump to the address specified by Rsrc The condition bit C is unchanged EIT occurrence None Encoding JM...

Page 99: ...into Rdest 2 The contents of the memory at the address specified by Rsrc are loaded into Rdest Rsrc is post incremented by 4 3 The contents of the memory at the address specified by Rsrc combined with...

Page 100: ...Function Load the 24 bit immediate value into register Rdest imm24 0x00ffffff Description LD24 loads the 24 bit immediate value into Rdest The immediate value is zero extended to 32 bits The condition...

Page 101: ...he byte data of the memory at the address specified by Rsrc and loads it into Rdest 2 LDB sign extends the byte data of the memory at the address specified by Rsrc combined with the 16 bit displacemen...

Page 102: ...rd data of the memory at the address specified by Rsrc and loads it into Rdest 2 LDH sign extends the halfword data of the memory at the address specified by Rsrc combined with the 16 bit displacement...

Page 103: ...dest signed short imm16 Description 1 LDI loads the 8 bit immediate value into Rdest The immediate value is sign extended to 32 bits 2 LDI loads the 16 bit immediate value into Rdest The immediate val...

Page 104: ...xtends the byte data from the memory at the address specified by Rsrc and loads it into Rdest 2 LDUB zero extends the byte data of the memory at the address specified by Rsrc com bined with the 16 bit...

Page 105: ...e halfword data from the memory at the address specified by Rsrc and loads it into Rdest 2 LDUH zero extends the halfword data in memory at the address specified by Rsrc com bined with the 16 bit disp...

Page 106: ...ster access is not accepted The LOCK bit is cleared by executing the UNLOCK instruction The LOCK bit is located in the CPU and operates based on the LOCK and UNLOCK instruc tions The user cannot direc...

Page 107: ...mulator and the portion corresponding to bits 8 through 15 of the accumulator is sign extended before addition The result of the addition is stored in the accumulator The high order 16 bits of Rsrc1 a...

Page 108: ...or and the portion corresponding to bits 8 through 15 of the accumulator is sign extended before addition The result of the addition is stored in the accumulator The low order 16 bits of Rsrc1 and Rsr...

Page 109: ...or and the portion corresponding to bits 8 through 15 of the accumulator is sign extended before addition The result of addition is stored in the accumulator The 32 bits of Rsrc1 and the high order 16...

Page 110: ...nd the portion corresponding to bits 8 through 15 of the accumulator is sign extended before the addition The result of the addition is stored in the accumulator The 32 bits Rsrc1 and the low order 16...

Page 111: ...64bit Rdest signed64bit Rsrc Rdest int tmp Description MUL multiplies Rdest by Rsrc and puts the result in Rdest The operands are treated as signed values The contents of the accumulator are destroyed...

Page 112: ...cation result is aligned with bit 47 in the accumulator and the portion corresponding to bits 0 through 15 of the accumulator is sign extended Bits 48 through 63 of the accumulator are cleared to 0 Th...

Page 113: ...sult is aligned with bit 47 in the accumulator and the portion corresponding to bits 0 through 15 of the accumulator is sign extended Bits 48 through 63 of the accumulator are cleared to 0 The low ord...

Page 114: ...LSB of the multiplication result is aligned with the LSB of the accumulator and the portion corresponding to bits 0 through 15 of the accumulator is sign extended The 32 bits of Rsrc1 and high order 1...

Page 115: ...B of the multiplication result is aligned with the LSB of the accumulator and the portion corresponding to bits 0 through 15 of the accumulator is sign extended The 32 bits of Rsrc1 and low order 16 b...

Page 116: ...fer instruction Move register Mnemonic MV Rdest Rsrc Function Transfer Rdest Rsrc Description MV moves Rsrc to Rdest The condition bit C is unchanged EIT occurrence None Encoding dest 0001 MV Rdest Rs...

Page 117: ...lator Mnemonic MVFACHI Rdest Function Transfer from accumulator to register Rdest int accumulator 32 Description MVFACHI moves the high order 32 bits of the accumulator to Rdest The condition bit C is...

Page 118: ...ulator Mnemonic MVFACLO Rdest Function Transfer from accumulator to register Rdest int accumulator Description MVFACLO moves the low order 32 bits of the accumulator to Rdest The condition bit C is un...

Page 119: ...umulator Mnemonic MVFACMI Rdest Function Transfer from accumulator to register Rdest int accumulator 16 Description MVFACMI moves bits16 through 47 of the accumulator to Rdest The condition bit C is u...

Page 120: ...ontrol register Mnemonic MVFC Rdest CRsrc Function Transfer from control register to register Rdest CRsrc Description MVFC moves CRsrc to Rdest The condition bit C is unchanged EIT occurrence None Enc...

Page 121: ...mulator Mnemonic MVTACHI Rsrc Function Transfer from register to accumulator accumulator 0 31 Rsrc Description MVTACHI moves Rsrc to the high order 32 bits of the accumulator The condition bit C is un...

Page 122: ...mulator Mnemonic MVTACLO Rsrc Function Transfer from register to accumulator accumulator 32 63 Rsrc Description MVTACLO moves Rsrc to the low order 32 bits of the accumulator The condition bit C is un...

Page 123: ...Rsrc CRdest Function Transfer from register to control register CRdest Rsrc Description MVTC moves Rsrc to CRdest If PSW CR0 is specified as CRdest the condition bit C is changed otherwise it is un ch...

Page 124: ...ic NEG Rdest Rsrc Function Negate Rdest 0 Rsrc Description NEG negates changes the sign of Rsrc treated as a signed 32 bit value and puts the result in Rdest The condition bit C is unchanged EIT occur...

Page 125: ...uction No operation Mnemonic NOP Function No operation Description NOP performs no operation The subsequent instruction then processed The condition bit C is unchanged EIT occurrence None Encoding NOP...

Page 126: ...ical NOT Mnemonic NOT Rdest Rsrc Function Logical NOT Rdest Rsrc Description NOT inverts each of the bits of Rsrc and puts the result in Rdest The condition bit C is unchanged EIT occurrence None Enco...

Page 127: ...st Rsrc Function Logical OR Rdest Rdest Rsrc Description OR computes the logical OR of the corresponding bits of Rdest and Rsrc and puts the result in Rdest The condition bit C is unchanged EIT occurr...

Page 128: ...t Rsrc unsigned short imm16 Description OR3 computes the logical OR of the corresponding bits of Rsrc and the 16 bit immediate value which is zero extended to 32 bits and puts the result in Rdest The...

Page 129: ...f 0x0000 7fff ffff 0000 tmp accumulator 0x0000 7fff ffff 0000 else if tmp 0xffff 8000 0000 0000 accumulator 0xffff 8000 0000 0000 else accumulator tmp 0xffff ffff ffff 0000 Description RAC rounds the...

Page 130: ...s 1 the bit is carried Bits 48 to 63 are cleared to zero 0000 7FFF FFFF 8000 positive value negative value 0000 7FFF FFFF 7FFF 0000 0000 0000 0000 FFFF 8000 0000 8000 FFFF 8000 0000 7FFF supposed sign...

Page 131: ...00 if 0x0000 7fff 0000 0000 tmp accumulator 0x0000 7fff 0000 0000 else if tmp 0xffff 8000 0000 0000 accumulator 0xffff 8000 0000 0000 else accumulator tmp 0xffff ffff 0000 0000 Description RACH rounds...

Page 132: ...is carried Bits 32 to 63 are cleared to zero 0000 7FFE 8000 0000 positive value negative value 0000 7FFE 7FFF 7FFF 0000 0000 0000 0000 FFFF 8000 8000 0000 FFFF 8000 7FFF FFFF supposed sign extended bi...

Page 133: ...M divides Rdest by Rsrc and puts the quotient in Rdest The operands are treated as signed 32 bit values The quotient is rounded toward zero and the quotient takes the same sign as the dividend The con...

Page 134: ...r Rdest unsigned Rdest unsigned Rsrc Description REMU divides Rdest by Rsrc and puts the quotient in Rdest The operands are treated as unsigned 32 bit values The condition bit C is unchanged When Rsrc...

Page 135: ...PC BPC 0xfffffffc Description RTE restores the SM IE and C bits of the PSW from the BSM BIE and BC bits and jumps to the address specified by BPC At this time because the BSM BIE and BC bits in the P...

Page 136: ...ion Transfer instructions Rdest signed short imm16 16 Description SETH load the immediate value into the 16 most significant bits of Rdest The 16 least significant bits become zero The condition bit C...

Page 137: ...SM IE anc C bits of PSW to 1 PSW imm8 0x000000ff Description Set the AND result of the value of b0 MSB b1 and b7 LSB of the 8 bit immediate value and bits SM IE and C of PSW to the corresponding SM I...

Page 138: ...Rdest Rsrc 31 Description SLL left logical shifts the contents of Rdest by the number specified by Rsrc shifting zeroes into the least significant bits Only the five least significant bits of Rsrc ar...

Page 139: ...on SLL3 left logical shifts the contents of Rsrc into Rdest by the number specified by the 16 bit immediate value shifting zeroes into the least significant bits Only the five least significant bits o...

Page 140: ...Logical left shift Rdest Rdest imm5 Description SLLI left logical shifts the contents of Rdest by the number specified by the 5 bit immediate value shifting zeroes into the least significant bits The...

Page 141: ...est Rsrc 31 Description SRA right arithmetic shifts the contents of Rdest by the number specified by Rsrc replicates the sign bit in the MSB of Rdest and puts the result in Rdest Only the five least s...

Page 142: ...6 31 Description SRA3 right arithmetic shifts the contents of Rsrc into Rdest by the number specified by the 16 bit immediate value replicates the sign bit in Rsrc and puts the result in Rdest Only th...

Page 143: ...shift Rdest signed Rdest imm5 Description SRAI right arithmetic shifts the contents of Rdest by the number specified by the 5 bit immedi ate value replicates the sign bit in MSB of Rdest and puts the...

Page 144: ...src 31 Description SRL right logical shifts the contents of Rdest by the number specified by Rsrc shifts zeroes into the most significant bits and puts the result in Rdest Only the five least signific...

Page 145: ...Description SRL3 right logical shifts the contents of Rsrc into Rdest by the number specified by the 16 bit immediate value shifts zeroes into the most significant bits Only the five least significant...

Page 146: ...Logical right shift Rdest unsigned Rdest imm5 31 Description SRLI right arithmetic shifts Rdest by the number specified by the 5 bit immediate value shift ing zeroes into the most significant bits The...

Page 147: ...dress specified by Rsrc2 2 ST increments Rsrc2 by 4 and stores Rsrc1 in the memory at the address specified by the resultant Rsrc2 3 ST decrements Rsrc2 by 4 and stores the contents of Rsrc1 in the me...

Page 148: ...1 Encoding src1 1010 src1 0010 0111 src2 0100 src2 disp16 src1 0010 0110 src2 src1 0010 0100 src2 ST Rsrc1 Rsrc2 ST Rsrc1 Rsrc2 ST Rsrc1 Rsrc2 ST Rsrc1 disp16 Rsrc2 INSTRUCTIONS 3 2 Instruction descri...

Page 149: ...of Rsrc1 in the memory at the address specified by Rsrc2 2 STB stores the least significant byte of Rsrc1 in the memory at the address specified by Rsrc combined with the 16 bit displacement The displ...

Page 150: ...at the address specified by Rsrc2 2 STH stores the LSB halfword of Rsrc1 to the memory of the address specified by Rsrc2 and then increments Rsrc2 by 2 3 STH stores the least significant halfword of...

Page 151: ...ion Subtract Mnemonic SUB Rdest Rsrc Function Subtract Rdest Rdest Rsrc Description SUB subtracts Rsrc from Rdest and puts the result in Rdest The condition bit C is unchanged EIT occurrence None Enco...

Page 152: ...Rdest Rsrc Function Subtract Rdest Rdest Rsrc C overflow 1 0 Description SUBV subtracts Rsrc from Rdest and puts the result in Rdest The condition bit C is set when the subtraction results in overflo...

Page 153: ...nsigned Rdest unsigned Rsrc C C borrow 1 0 Description SUBX subtracts Rsrc and C from Rdest and puts the result in Rdest The condition bit C is set when the subtraction result cannot be represented by...

Page 154: ...n Trap occurrence BPC PC 4 BSM SM BIE IE BC C IE 0 C 0 call_trap_handler imm4 Description TRAP generates a trap with the trap number specified by the 4 bit immediate value IE and C bits are cleared to...

Page 155: ...on clears the LOCK bit to 0 in addition to the simple storage operation The LOCK bit is internal to the CPU and cannot be accessed except by using the LOCK and UNLOCK instructions The user cannot dire...

Page 156: ...ion value Rdest float unsigned int Rsrc Description UTOF converts the 32 bit unsigned integer stored in Rsrc to a floating point single precision value and the result is stored in Rdest The result is...

Page 157: ...src Function Exclusive OR Rdest unsigned Rdest unsigned Rsrc Description XOR computes the logical XOR of the corresponding bits of Rdest and Rsrc and puts the result in Rdest The condition bit C is un...

Page 158: ...est unsigned Rsrc unsigned short imm16 Description XOR3 computes the logical XOR of the corresponding bits of Rsrc and the 16 bit immediate value which is zero extended to 32 bits and puts the result...

Page 159: ...xadecimal Instraction Code APPENDIX 2 Instruction List APPENDIX 3 Pipeline Processing APPENDIX 4 Instruction Execution Time APPENDIX 5 IEEE754 Specification Overview APPENDIX 6 M32R FPU Specification...

Page 160: ...I MULLO MULWHI MULWLO MACHI MACLO MACWHI MACWLO Rsrc1 Rsrc2 Rsrc1 Rsrc2 Rsrc1 Rsrc2 Rsrc1 Rsrc2 Rsrc1 Rsrc2 Rsrc1 Rsrc2 Rsrc1 Rsrc2 Rsrc1 Rsrc2 ADDI Rdest imm8 Rdest imm5 Rdest imm5 Rdest imm5 SRLI SR...

Page 161: ...SLL3 Rdest Rsrc imm16 LDI Rdest imm16 LDB Rdest disp16 Rsrc LDUB Rdest disp16 Rsrc LDH Rdest disp16 Rsrc LDUH Rdest disp16 Rsrc LD Rdest disp16 Rsrc BEQZ Rsrc pcdisp16 BNEZ Rsrc pcdisp16 BLTZ Rsrc pcd...

Page 162: ...src 0 PC PC sh pcdisp16 2 BLTZ Rsrc pcdisp16 if Rsrc 0 PC PC sh pcdisp16 2 BNC pcdisp8 if C PC PC sb pcdisp8 2 BNC pcdisp24 if C PC PC s24 pcdisp24 2 BNE Rsrc1 Rsrc2 pcdisp16 if Rsrc1 Rsrc2 PC PC sh p...

Page 163: ...mm8 LDUB Rdest disp16 Rsrc Rdest ub Rsrc sh disp16 LDUB Rdest Rsrc Rdest ub Rsrc LDUH Rdest disp16 Rsrc Rdest uh Rsrc sh disp16 LDUH Rdest Rsrc Rdest ub Rsrc LOCK Rdest Rsrc LOCK 1 Rdest s Rsrc MACHI...

Page 164: ...6 31 SRAI Rdest imm5 Rdest s Rdest imm5 SRL Rdest Rsrc Rdest u Rdest Rsrc 31 SRL3 Rdest Rsrc imm16 Rdest u Rsrc imm16 31 SRLI Rdest imm5 Rdest u Rdest imm5 ST Rsrc1 disp16 Rsrc2 s Rsrc2 sh disp16 Rsrc...

Page 165: ...rd typedef unsigned int u 32 bit unsigned integer word typedef signed short sh 16 bit signed integer halfword typedef unsigned short uh 16 bit unsigned integer halfword typedef signed char sb 8 bit si...

Page 166: ...cuted at the same time as the E or E1 stage 6 stages IF D E1 E2 WB Pipeline Stage FPU instruction excluding FMADD FMSUB The E1 and E2 stages cannot be executed at the same time as the E stage The E1 s...

Page 167: ...lf of the stage E stage execution stage Operations and address calculations OP are processed in the E stage If an operation result from the previous instruction is required bypass process BYP is perfo...

Page 168: ...WB IF D WB E D WB E IF D WB E Case 2 Load store instructions to destination are accessed in 1 cycle continuously IF D E WB ST R0 R15 ST R1 R15 LDI R0 1 ADD R0 R1 OR R0 R2 CMP R0 R3 IF D WB MEM2 MEM1...

Page 169: ...R0 R5 R6 FSUB R1 R6 R7 IF D E2 E1 WB E2 E1 WB E2 E1 WB E2 IF D FMUL R2 R7 R8 FCMP R0 R0 R3 IF D IF D EA WB FMADD R0 R5 R6 FMADD R1 R6 R7 IF D EM E2 EA WB EM E2 EA WB EM E2 EA WB EM E2 IF D FMADD R2 R...

Page 170: ...DIV R1 R2 E E IF D stall WB ADD R3 R4 E stall IF D WB E stall stall IF D stall WB E stall ADD R5 R6 ADD R7 R8 Case 2 An instruction which requires more than 1 cycle for its operand access is executed...

Page 171: ...ass process branch instruction is executed stall stall Case 4 The subsequent instruction uses an operand read from the memory IF D E WB LD R1 R2 IF D WB MEM2 MEM1 ADD R3 R1 stall stall IF Bypass proce...

Page 172: ...D E1 WB FADD R0 R1 R2 IF D WB E E2 MVFC R3 FPSR stall stall IF D E1 WB FADD R0 R1 R2 IF D E2 WB E1 E2 FADD R3 R0 R4 stall stall IF D EM WB FMADD R0 R1 R2 IF D E2 WB EA EA E2 EM FMADD R0 R3 R4 stall s...

Page 173: ...R0 R1 ADD R5 R6 FADD R2 R3 R4 FADD R7 R8 R9 Case 10 The FMADD FMSUB instructions run consecutively with the integer instruction with no register dependency IF D E WB IF D WB E2 D WB E stall stall IF D...

Page 174: ...E1 stall IF D E2 WB EA EM EA EM stall IF Case 13 The FPU and FMADD FMSUB instructions run consecutively with register dependency FADD R0 R1 R10 FADD R5 R6 R11 FMADD R2 R3 R4 FMADD R7 R8 R9 IF D E1 E2...

Page 175: ...ge instruction IF D E MEM1 MEM2 WB load instruction LD LDB LDUB LDH LDUH LOCK R note 1 1 1 R note 1 1 1 store instruction ST STB STH UNLOCK R note 1 1 1 W note 1 1 1 note 2 BSET BCLR instructions R no...

Page 176: ...positive by adding 127 to a single precision value or 1023 to a double precision value biased exponent f Fraction Represents the fraction field of the value Using these symbols the floating point val...

Page 177: ...Denormalized Numbers Denormalized numbers represent numbers values that have an absolute value less than 1 0 0 x 2 126 Single precision denormalized numbers are expressed as follows 1 s x 0 f x 2 126...

Page 178: ...inity and Round toward Zero are used for interval arithmetic to insure precision Appendix 5 3 Exceptions IEEE754 allows the following 5 exceptions The floating point status register is used to determi...

Page 179: ...respective conditions in which each IXCT occurs Appendix Table 5 3 3 Operation Results and Respective Conditions for IXCT Exception Result Occurrence Condition when the IXCT EIT when the IXCT EIT pro...

Page 180: ...of result is exclusive OR EXOR of signs of divider and dividend Definition of Terms Exception Special conditions generated by execution of floating point instructions The corresponding enable bits of...

Page 181: ...DD rounds both FMUL and FADD according to the setting of the FPSR RM field However the result of the FMADD or FMSUB instruction in Step 1 multiply stage is not rounded according to the setting of FPSR...

Page 182: ...1 Operation Result due to OVF Exception for immediate values if an overflow occurs due to Overflow Exclusion when the EIT processing is masked Note 2 In Step 1 the rounding mode is set to Round toward...

Page 183: ...is EIT occurs number 0 completed R0 maintained Infinity R0 maintained Denormalized Same as above Same as above number QNaN Same as above Same as above SNaN EV 0 Same as above IVLD occurs EIT occurs R...

Page 184: ...n EV 1 IVLD occurs Type of R0 Condition FMUL FADD Operation FMADD Operation Normalized EIT occurs when FMUL is EIT occurs number 0 completed R0 maintained Infinity R0 maintained Denormalized DN 0 Same...

Page 185: ...aintained SNaN When EX 1 IXCT occurs Type of R0 Condition FMUL FADD Operation FMADD Operation Normalized EIT occurs when FMUL is EIT occurs number 0 completed R0 maintained Infinity R0 maintained Deno...

Page 186: ...1 Rsrc2 Rdest SNaN and QNaN SNaN converted to QNaN Note 1 Both SNaN Rsrc2 converted to QNaN Note 1 Both QNaN Rscr2 SNaN and actual number SNaN converted to QNaN Note 1 QNaN and actual number QNaN Neit...

Page 187: ...e high order halfword of the word and data with MSB of 1 may be aligned to the following halfword In this case the M32R family upward compatible CPU recognizes the 16 bit instruction and the data as a...

Page 188: ...APPENDICES APPENDICES 30 M32R FPU Software Manual Rev 1 01 This page left blank intentionally APPENDIX 7 Appendix 7 Precautions...

Page 189: ...INDEX...

Page 190: ...7 BGEZ 3 18 BGTZ 3 19 BL 3 20 BLEZ 3 21 BLTZ 3 22 BNC 3 23 BNE 3 24 BNEZ 3 25 BRA 3 26 JL 3 59 JMP 3 60 NOP 3 87 C Compare instructions 2 4 CMP 3 30 CMPI 3 31 CMPU 3 32 CMPUI 3 33 Condition Bit Regist...

Page 191: ...Operand List 3 2 P PC relative pcdisp 1 14 3 2 Processor Status Register PSW 1 3 1 4 Program Counter PC 1 11 E EIT related instructions 2 8 RTE 3 97 TRAP 3 116 F Floating point instruction 2 11 FADD...

Page 192: ...t and register update 1 15 3 2 Register relative indirect disp R 1 15 3 2 S Shift instructions 2 5 SLL 3 100 SLL3 3 101 SLLI 3 102 SRA 3 103 SRA3 3 104 SRAI 3 105 SRL 3 106 SRL3 3 107 SRLI 3 108 Stack...

Page 193: ...MICROCOMPUTER SOFTWARE MANUAL M32R FPU Publication Data Rev 1 00 Jan 08 2003 Rev 1 01 Oct 31 2003 Published by Sales Strategic Planning Div Renesas Technology Corp 2003 Renesas Technology Corp All ri...

Page 194: ...1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan M32R FPU REJ09B0112 0101Z Software Manual...

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