Renesas M32R-FPU, Software Manual

Page: 164 / 194

APPENDICES
APPENDICES-6
M32R-FPU Software Manual (Rev.1.01)
mnemonic function condition bit (C)
NEG Rdest,Rsrc Rdest = 0 - Rsrc
–
NOP /*no-operation*/
–
NOT Rdest,Rsrc Rdest =
~
Rsrc
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OR Rdest,Rsrc Rdest = Rdest | Rsrc
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OR3 Rdest,Rsrc,#imm16 Rdest = Rsrc | (uh)imm16
–
RAC Round the 32-bit value in the accumulator
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RACH Round the 16-bit value in the accumulator
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REM Rdest,Rsrc Rdest = (s)Rdest % (s)Rsrc
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REMU Rdest,Rsrc Rdest = (u)Rdest % (u)Rsrc
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RTE PC = BPC & 0xfffffffc, change
PSW[SM,IE,C] = PSW[BSM,BIE,BC]
SETH Rdest,#imm16 Rdest = imm16 << 16
–
SETPSW #imm8 PSW | = imm8&0x000000ff change
SLL Rdest,Rsrc Rdest = Rdest << (Rsrc & 31)
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SLL3 Rdest,Rsrc,#imm16 Rdest = Rsrc << (imm16 & 31)
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SLLI Rdest,#imm5 Rdest = Rdest << imm5
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SRA Rdest,Rsrc Rdest = (s)Rdest >> (Rsrc & 31)
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SRA3 Rdest,Rsrc,#imm16 Rdest = (s)Rsrc >> (imm16 & 31)
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SRAI Rdest,#imm5 Rdest = (s)Rdest >> imm5
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SRL Rdest,Rsrc Rdest = (u)Rdest >> (Rsrc & 31)
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SRL3 Rdest,Rsrc,#imm16 Rdest = (u)Rsrc >> (imm16 & 31)
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SRLI Rdest,#imm5 Rdest = (u)Rdest >> imm5
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ST Rsrc1,@(disp16,Rsrc2) *(s *)(Rsrc2+(sh)disp16) = Rsrc1
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ST Rsrc1,@+Rsrc2 Rsrc2 += 4, *(s *)Rsrc2 = Rsrc1
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ST Rsrc1,@-Rsrc2 Rsrc2 -= 4, *(s *)Rsrc2 = Rsrc1
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ST Rsrc1,@Rsrc2 *(s *)Rsrc2 = Rsrc1
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STB Rsrc1,@(disp16,Rsrc2) *(sb *)(Rsrc2+(sh)disp16) = Rsrc1
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STB Rsrc1,@Rsrc2 *(sb *)Rsrc2 = Rsrc1
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STH Rsrc1,@(disp16,Rsrc2) *(sh *)(Rsrc2+(sh)disp16) = Rsrc1
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STH Rsrc1,@Rsrc2 *(sh *)Rsrc2 = Rsrc1
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STH Rsrc1,@Rsrc2+ *(sh *)Rsrc2 = Rsrc1, Rsrc2 += 2
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SUB Rdest,Rsrc Rdest = Rdest - Rsrc
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SUBV Rdest,Rsrc Rdest = Rdest - Rsrc change
SUBX Rdest,Rsrc Rdest = Rdest - Rsrc - C change
TRAP #n PSW[BSM,BIE,BC] = PSW[SM,IE,C] change
PSW[SM,IE,C] = PSW[SM,0,0]
Call trap-handler number-n
UNLOCK Rsrc1,@Rsrc2 if(LOCK) { *(s *)Rsrc2 = Rsrc1; } LOCK=0
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UTOF Rdest,Rsrc Rdest = (float)(unsigned int) Rsrc;
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XOR Rdest,Rsrc Rdest = Rdest ^ Rsrc
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XOR3 Rdest,Rsrc,#imm16 Rdest = Rsrc ^ (uh)imm16
–
APPENDIX 2
Appendix 2 Instruction List