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VMEbus Interrupt Handling

All VMEbus interrupt signals, IRQ1 to IRQ7, can be enabled/disabled separately using
jumper field WA1 to WA7, as shown in Figure 32. The position of the jumpers are
shown below in Figure 31.

When a jumper is inserted an incoming IRQ signal will be acknowledged by the CPU;
removing a jumper disables the equivalent IRQ signal. In the default condition, all IRQ
signals will be acknowledged.

Figure 31 Location of VMEbus Interrupt Jumper

Figure 32 VMEbus Interrupt Jumper Field

WA 1-7

WA7 WA6 WA5 WA4 WA3 WA2 WA1

I/O Interrupt

Control Logic

5V

74LS641-1

J68

+5V

9X4K7

DIR

24

25
26

27

28

29

30

1

ENA
A1

A2

A3

A4

A5
A6

A7
A8

WA7

WA6

WA5

WA4

WA3

WA2

WA1

IRQ7
IRQ6

IRQ5

IRQ4

IRQ3

IRQ2
IRQ1

B1

B2

B3

B4

B5

B6

B7
B8

IRQ7

IRQ6

IRQ5

IRQ4

IRQ3

IRQ2

IRQ1

2

3

4

5

6
7

8

9

10

IRQ 2

IRQ3
IRQ4
IRQ5

IRQ6

IRQ7

IRQ1

RN1

P1 Row B

PME68-1B Manual

Page 66 Issue 5

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Summary of Contents for PME 68-1B

Page 1: ...lessey Company plc 1988 Issue 4 Radstone Technology plc 1989 This publication is issued to provide outline information only which unless agreed by the Company in writing maynot be used applied or repr...

Page 2: ...ntified by a label fitted to the component side of P1 This publication describes the PME 68 1B at Revision state Rev 2 all letter codes Unique board serial number MADE IN ENGLAND SERIAL NUMBER REV NO...

Page 3: ...al I O 18 Terminal Interface 18 Address Assignment of Terminal Interface 20 Remote Interface 20 Address Assignment Remote Interface 21 Host Interface 21 Address Assignment Host Interface 22 Serial I O...

Page 4: ...Link Settings 47 RAM PROM EPROM Area 52 System Area 52 System Connections 52 User Area 54 Access Speed Select 56 Local I O and Control Devices 57 Terminal Interface 57 Remote Interface 58 Host Interfa...

Page 5: ...9 DATA CONVERSION DC 89 DUMP MEMORY DU 90 GO EXECUTE PROGRAM GO 91 GO DIRECT TO EXECUTE PROGRAM GD 91 GO UNTIL BREAKPOINT GT 92 HELP HE 93 LOAD OBJECT FILE LO 94 MEMORY DISPLAY MD 95 MEMORY MODIFY MM...

Page 6: ...ation Software Examples 116 Data Transfer From and To an ACIA 116 Output of One Line to the REMOTE ACIA 116 Input of One Line from the Remote ACIA 117 Initialisation of the Real time Clock 118 Address...

Page 7: ...supplied with the board This powerful software package can be used for program development and debugging The PME 68 1B is supported by Radstone VERSAdos operating system This software provides for Rea...

Page 8: ...Figure 1 The PME 68 1B Board Photograph not available in PDF PME 68 1B Manual Page 2 Issue 5...

Page 9: ...Chapter 4 plus details of the PME68 Monitor in Chapter 5 Certain application specific boards are factory configured for individual users For rea sons of confidentiality detailed reference is not made...

Page 10: ...Figure 2 The PME 68 1B Front Panel RESET ABORT HALT LED REMOTE TERMINAL HOST Port 3 P5 Port 1 P4 P3 Port 2 PME 68 1B RADSTONE TECHNOLOGY PME 68 1B Manual Page 4 Issue 5...

Page 11: ...e Wire VMEbus Arbiter Dynamic RAM 128k byte 512k byte Parallel I O Interface VMEbus Interface Port 3 P5 Port 1 P4 Port 2 P3 REMOTE TERMINAL HOST RESET ABORT HALT Area Interrupt and Control Logic Syste...

Page 12: ...Figure 4 Component Layout Diagram P5 P4 P3 BAT PME 68 1B Manual Page 6 Issue 5...

Page 13: ...or with 10 MHz clock variants 101 and 103 Fully implemented VMEbus interface 128k bytes of DRAM using 64k bit devices 512k bytes DRAM using 256k bit devices Access time 280ns Distributed refresh 300n...

Page 14: ...cated at the rear of the board gives access to the Parallel Interface and Timer module PIT The PIT provides 24 I O lines and 4 control lines plus a 24 bit timer with 5 bit prescaler P2 can be configur...

Page 15: ...O Three 6850 type ACIAs configured as RS 232C interfaces Strap selectable baud rates 110 to 9600 baud or 440 to 38400 baud Real Time Clock 58167A programmable real time clock optional battery back up...

Page 16: ...Mechanical Shock 20g for 6ms half sine when mounted in a suitable racking system MTBF The calculated mean time between failures for the PME 68 1B is 80 000 hrs The failure rates used in this calculat...

Page 17: ...1B is shown in Figure 2 and contains 1 Reset Switch a toggle switch that is user defined to carry out a general VMEbus reset or a reset of all on board devices only 2 Abort Switch a toggle switch use...

Page 18: ...registers In addition all 16 registers may be used for word and long word address operations or as index registers Table 1 shows the vector layout of the 68000 Features of the 68000 CPU include 8 x 3...

Page 19: ...040 SD Unassigned Reserved 95 05F 24 96 060 SD Spurious Interrupt 25 100 064 SD Level 1 Interrupt Auto vector 26 104 068 SD Level 2 Interrupt Auto vector 27 108 06C SD Level 3 Interrupt Auto vector 2...

Page 20: ...RAM Area 512k byte variants 102 and 103 07F FFF 080 000 080 000 080 007 used for stack 1 Prog Counter data SYSTEM EPROM Area 128k byte 09F FFF 0A0 000 USER EPROM Area 128k byte 0BF FFF 0C0 041 RS 232C...

Page 21: ...h is fully asynchronous to the LOCAL and VMEbuses The refresh process is completely transparent to the user When a refresh request is pending a delay of 300ns maximum is required before attempting to...

Page 22: ...k x 8 bit 8 kbytes total EPROM 2764 8k x 8 bit 16 kbytes total EPROM 27128 16k x 8 bit 32 kbytes total EPROM 27256 32k x 8 bit 64 kbytes total EPROM 27512 64k x 8 bit 128 kbytes total The PME68 Monito...

Page 23: ...ROM 27128 16k x 8 bit 32k bytes total EPROM 27256 32k x 8 bit 64k bytes total EPROM 27512 64k x 8 bit 128k bytes total SRAM 6264 8k x 8 bit 16k bytes total SRAM 62256 32k x 8 bit 64k bytes total Chip...

Page 24: ...the female 25 pin D type sub connector assigned to it The serial I O controllers are 6850 devices These are Asynchronous Communication Interface Adaptor ACIA chips Selected signals associated with eac...

Page 25: ...4 Figure 6 Terminal Interface The interface is enabled in Transparent Mode by activating the RTST line 6850 IRQP4 D8 D9 D10 D11 D12 D13 D14 D15 A11 A7 5V CS6800 E R W 7 22 21 20 19 18 17 16 15 11 8 1...

Page 26: ...ata Set Ready DSR 7 X X Signal GND 8 X Data Carrier Detect DCD 9 X X Signal GND 20 X Data Terminal Ready DTR Remote Interface Port 3 is an RS 232C compatible interface on connector P5 It is defined as...

Page 27: ...o correction or modification is done by the PME68 1B Figure 7 is a schematic of this configuration When the user types a valid stop character sequence the CPU recognises it stops transmission of the f...

Page 28: ...0041 R Status Register 0C0041 W Control Register 0C0043 R Receive Data Register 0C0043 W Transmit Data Register Table 3 Signal Assignment Host Interface P3 Pin Input Output Signal 1 X X Protective GND...

Page 29: ...Host Computer in Transparent Mode HOST 2 3 4 5 6 8 20 1 7 2 3 4 5 6 8 20 1 7 2 3 4 5 6 8 20 1 7 Tx Data Rx Data RTS CTS DSR DCD 2 3 4 5 6 8 20 1 7 PME 68 1B P3 P4 CPU I N T E R F A C E TERMINAL PME68...

Page 30: ...000ns min 2000ns max Interrupt request level 4 Interrupt handling Fixed IRQ vector 28 Address 000070 Host Interface Port 2 Connector P3 Start address 0C0041 End address 0C0043 Access mode Byte Only Re...

Page 31: ...ddress 00006C ACIA Access Time The ACIA is a controller device from the 6800 family Access cycles are controlled by the Processor signals VMA VPA and the E signal To initiate a transfer the Processor...

Page 32: ...the following features 1 10000 of a second through month counter 24 hour clock 56 bits of RAM with comparator to compare RTC data with RAM data Interrupt output with 8 possible interrupt signals Power...

Page 33: ...n 0C0401 R W Counter Ten thousandths of seconds 0C0403 R W Counter Hundredths and tenths of seconds 0C0405 R W Counter Seconds 0C0407 R W Counter Minutes 0C0409 R W Counter Hours 0C040B R W Counter Da...

Page 34: ...tional 8 bit and 16 bit Selectable handshaking options This is done via the software and reference should be made to a PIT data sheet 24 bit programmable timer with 5 bit prescaler Software programmab...

Page 35: ...h CPRH 0E0029 R W N Counter Preload Register Middle CPRM 0E002B R W N Counter Preload Register Low CPRL 0E002F R N Count Register High CNTRH 0E0031 R N Count Register Middle CNTRM 0E0033 R N Count Reg...

Page 36: ...compatible printer with the handshake protocol under full software control See Chapter 4 for further details Figure 9 below shows how the PIT may be user configured as a Centronics type interface The...

Page 37: ...the incoming interrupt is greater than the current processor priority the exception processing sequence is started On board Interrupt Sources PME68 1B boards contain six possible on board interrupt so...

Page 38: ...cated by the red HALT LED on the front panel A link may be removed so that ACFAIL has no affect on the cpu see Chapter 4 Interrupt Exception Sequence Once the interrupt exception sequence has started...

Page 39: ...0 to FC2 are function code signals from the 68000 The vector from the interrupting device is placed onto data bits D0 to D7 and is translated by the CPU into the address of the interrupt handling rout...

Page 40: ...A8 V6 A9 V7 A10 0 A15 Table 9 Auto interrupt Vector Table Absolute Vector Corresponding Address Number Interrupt Level 000060 24 Spurious Interrupt 000064 25 Level 1 Auto interrupt Vector 000068 26 2...

Page 41: ...ve Interrupt Acknowledge IACK signal informs all cards within the system that the current read cycle is an interrupt vector acquisition This signal is connected at slot 1 of the motherboard to the Int...

Page 42: ...l the Data Transfer Bus DTB The DTB is the transport medium for all data and includes the address address modifier strobe control and acknowledge signals The Arbiter must reside in slot number 1 of th...

Page 43: ...ven low by a VME module to inform the Arbiter that it requires control of the DTB Data Transfer Bus When the current bus master releases control of the bus and a bus request is pending a new arbitrati...

Page 44: ...ation mode a release on BCLR The maximum continuous time available as bus master is defined by on board jumpers as 30 60 or 300ms An arbitration cycle on every bus cycle can also be selected Refer to...

Page 45: ...located on the front panel Figure 2 It can be used to carry out a RESET of all devices on the PME 68 1B board CPU PIT ACIA or produce a VME SYSRESET signal This carries out a general RESET of all boar...

Page 46: ...2E H L H H H L Reserved 2D H L H H L H Short Supervisory I O Access 2C H L H H L L Reserved 2B H L H L H H Reserved 2A H L H L H L Reserved 29 H L H L L H Short Non Privileged I O Access 28 H L H L L...

Page 47: ...to FFFFFF 000000 100000 are employed by on board memory and addresses Refer to Chapter 4 Bus Error Function A time out counter is used to provide an error handling function The external VMEbus Error B...

Page 48: ...3IN SYSFAIL 11 GND BG3OUT BERR 12 DS1 BR0 SYSRESET 13 DS0 BR1 LWORD 14 WRITE BR2 AM5 15 GND BR3 A23 16 DTACK AM0 A22 17 GND AM1 A21 18 AS AM2 A20 19 GND AM3 A19 20 IACK GND A18 21 IACKIN SERCLK A17 22...

Page 49: ...1 PA6 22 PA5 23 PA4 24 PA3 25 PA2 LK56 26 PA1 LK57 27 PA0 LK53 28 LK58 LK55 29 LK50 LK54 30 LK51 LK52 31 5V 5V 32 5V 5V Note PA0 PA7 PB0 PB7 PC0 PC7 H1 H4 are all signals from the PIT J50 LK50 RX 51 T...

Page 50: ...gnal GND 20 Data Terminal Ready DTR P4 P5 Pin Assignments Pin Signal 1 Protective GND connected to signal GND 2 Transmit Data TXD 3 Receive Data RXD 4 Request to Send RTS 5 Clear to Send CTS 6 Data Se...

Page 51: ...n the monitor A standard RS 232C interface cable is fitted with two 25 pin male connectors The user should check the signal line assignment of all peripheral devices with those of the PME68 1B to avoi...

Page 52: ...ncinerate Do not attempt to charge the battery No attempt should be made to open the battery or pierce the casing Batteries should be stored in a dry location at normal room temperature with minimal t...

Page 53: ...e board link areas are shown in Figure 14 NOTE The link settings shown here are for general guidance some links listed will not be present on all board variants Table 12 Link Settings Link Pin connect...

Page 54: ...e WK1 Table 13 Variant Link Settings Variant Standard Versados Wide Temp User Specific Configuration Description 10 20 30 31 32 33 BR18 1 3 2 3 1 3 2 3 1 3 2 3 1 3 2 3 1 3 2 3 LK50 55 OUT OUT OUT IN I...

Page 55: ...DCD BR14 1 20 2 19 3 18 Asserting CTS DSR Pin 9 com 4 17 5 16 6 15 7 14 DCD from DTR 8 13 9 12 10 11 Terminal Interface P4 GND Rx Tx RTS BR34 1 2 RS232 Set as DCE CTS DSR DCD BR15 1 20 2 19 3 18 Asse...

Page 56: ...Figure 14 Link Areas BAT PME68 1B Manual Page 50 Issue 5...

Page 57: ...Blank Page PME68 1B Manual Page 51 Issue 5...

Page 58: ...OM 2732 2764 128 27256 27512 6264 62256 PIN 1 O C Vcc Vcc A16 O C A15 PIN 26 Vcc A14 A14 A14 Vcc A14 PIN 27 O C Vcc A15 A15 R W R W System Connections Table 17 System Area Jumper Field Settings Device...

Page 59: ...Figure 15 Location of System EPROM Area 1 2 3 4 1 2 3 4 WC1 WC2 PME68 1B Manual Page 53 Issue 5...

Page 60: ...Area Jumper Settings Device Type Device WD1 to WD2 Connection Pin 2732 EPROM 26 WD1 1 WD2 2 Vcc 27 WD1 2 O C 1 WD1 4 O C 2764 27128 EPROM 26 WD1 1 WD2 1 A14 27 WD1 2 WD2 2 Vcc Default 1 WD1 4 WD2 2 Vc...

Page 61: ...as A1 Care must be exercised when dealing with memory chips and other peripheral devices which may identify the least significant address bit as A0 J25 and J41 JEDECS Pin 26 J25 and J41 JEDECS Pin 27...

Page 62: ...he location of BR6 and BR7 Table 19 Access Speed Selection Jumper Jumper Access Times Device Closed Closed ns Access on BR7 on BR6 Min Max Times ns 2 3 2 3 62 125 60 2 3 2 4 125 188 125 2 3 2 1 188 25...

Page 63: ...er block BR15 see Figure 19 Figure 19 Location of Terminal Interface Jumper Figure 20 Terminal Interface 6850 IRQP4 D8 D9 D10 D11 D12 D13 D14 D15 A11 A7 5V CS6800 E R W 7 22 21 20 19 18 17 16 15 11 8...

Page 64: ...ote Interface Jumper Figure 22 Remote Interface BR33 10 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 19 20 BR14 6850 IRQPS D0 D1 D2 D3 D4 D5 D6 D7 A1 A8 5V CS6800 E R W 7 22 21 20 19 18 17 16 15 11 8 10...

Page 65: ...ure 23 Figure 23 Location of Host Interface Jumpers Figure 24 Host Interface BR16 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 BR35 6850 IRQP3 D0 D1 D2 D3 D4 D5 D6 D7 A1 A6 5V CS6800 E R W 7 22 21 20 19 18...

Page 66: ...es listed in Table 20 available A jumper between pins 1 and 2 make the baud rates detailed in Table 21 available Any number of connections can be made in areas WF1 and WF2 Table 20 Baud Rate Selector...

Page 67: ...ices 3 2 1 BR12 WF3 WF1 WF2 4 3 2 1 4 3 2 1 3 2 1 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 WF1 WF2 TINP1 TINP2 TINP3 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 1 1 2 2 3 3 4 1 2 3 4 RESET X1 X0 RSB...

Page 68: ...ions are set by LK60 and B200 LK60 B200 RTC only 2 3 IN PIT PC3 only 1 2 IN Figure 27 Location of the RTC Jumper and RTC Chip J63 B200 1 2 J51 3 2 1 LK60 BAT NOTE PIT PC3 by default interrupts on leve...

Page 69: ...ty of 48mA This allows a cable length of approximately 5 metres 16 feet to the printer The signal assignment of the PIT is given in Figure 29 The location of BR18 jumper is shown in Figure 28 Chapter...

Page 70: ...68230 A1 A2 A3 A4 A5 H3 5V BR18 1 2 3 IRQPIT 5V 680 R8 J50 P2A 5 P2A 14 P2A 19 P2A 28 P2C28 P2C 30 P2C 7 27 26 25 24 23 22 21 20 18 17 16 15 13 12 11 10 9 8 7 6 1 2 3 4 1 2 3 4 PA0 P2A PA1 P2A PA2 P2A...

Page 71: ...to 1 ACFAIL from Receiver 2 IRQ6 3 HALT of 68000 CPU If a connection is made between pins 1 and 3 the on board CPU will stop all activities immediately after the ACFAIL signal is asserted The Red HALT...

Page 72: ...lent IRQ signal In the default condition all IRQ signals will be acknowledged Figure 31 Location of VMEbus Interrupt Jumper Figure 32 VMEbus Interrupt Jumper Field WA 1 7 WA7 WA6 WA5 WA4 WA3 WA2 WA1 I...

Page 73: ...nections between WI1 1 and WI1 3 WI4 2 and WI4 3 WB1 1 and WB2 1 Figure 34 shows BRx BGxIN and BGxOUT jumper fields the location of the jumpers is shown below in Figure 33 Figure 33 Location of On boa...

Page 74: ...to WI1 3 WI2 2 to WI3 2 WI4 2 to WI3 2 WI2 3 to WI3 3 WI4 2 to WI4 3 WI2 3 to WI3 3 Bus Release Functions PME68 1B provides for a RAT Release After Time Out function and in slave arbitra tion mode rel...

Page 75: ...defines whether the board drives receives or ignores the VMEbus signal SYSRESET Table 22 lists all permitted jumper settings and the corresponding modes Figure 36 shows the location of jumper field B...

Page 76: ...serted the SYSFAIL signal is ignored Figure 37 Location of SYSFAIL Jumper Field BR19 BCLR Signal The PME 68 1B only supports single level arbitration therefore a BCLR signal is not generated However t...

Page 77: ...the default condition Figure 40 illustrates the jumper circuit arrangement The position of the short I O jumpers are shown on the location diagram Figure 39 Figure 39 Location of Short I O Jumpers The...

Page 78: ...3 3 A21 OUT WH1 4 WH3 4 A20 OUT WH2 1 WH4 1 A19 OUT WH2 2 WH4 2 A18 OUT WH2 3 WH4 3 A17 OUT WH2 4 WH4 4 A16 OUT Default Short I O Start Address FF0000 End Address FFFFFF Figure 40 Short I O Comparator...

Page 79: ...1 to 2 BR28 1 to 2 and 3 to 4 WK1 1 to WK1 2 Table 24 lists possible time out values and the jumper settings required Figure 41 shows the location of the jumper fields Table 24 Time Out Counter Setti...

Page 80: ...Figure 41 Location of BERR Jumpers 1 2 3 4 WK1 WK2 BR26 2 3 1 BAT PME68 1B Manual Page 74 Issue 5...

Page 81: ...rs During program development a dynamic assembler disassembler function is used In this mode the source program is not saved Each instruction is translated into the proper op code and stored in memory...

Page 82: ...eakpoint Display monitor commands Load object file Display memory Modify memory Set memory starting at add with data1 data2 Remove breakpoint Detach printer Offset Attach printer Set display port form...

Page 83: ...esses to terminate resets the CPU and the parallel I O devices and restarts the resident firmware The RESET switch may be used if all else fails ABORT Switch The ABORT switch is SW2 on the CPU front p...

Page 84: ...ine 1010 Emulator 11 44 02C SD Line 1111 Emulator 12 48 030 SD Unassigned reserved 13 52 034 SD Unassigned reserved 14 56 038 SD Unassigned reserved 15 60 03C SD Uninitialised Interrupt Vector 16 64 0...

Page 85: ...T vectors from 100 3FF are preset with the message TRAP ERROR The hardware interrupt level assignment is described in Chapter 3 As the Monitor shares resources with the user application program the co...

Page 86: ...rt of the Monitor complete reinitialisation is done via an indirect jump to the initial start address 4 Coldstart calls i e pressing the RESET switch should be handled with care as the old status of t...

Page 87: ...M area must be accessed with care to ensure proper operation of PME Monitor 000000 System EPROM 000007 000008 System RAM 000FFF 001000 User RAM 01FFFF 020000 Reserved 080007 080008 System EPROM 09FFFF...

Page 88: ...MONITOR v r where v r is the version revised number Whenever the monitor prompt appears a valid command may be entered at the terminal System Operation The user can now enter any command supported by...

Page 89: ...lays the entire line d RETURN carriage return enters the command line and causes processing to begin e BREAK aborts commands that perform any console I O and return to the input Command Line Format No...

Page 90: ...the user it is output by PME68 Monitor to the terminal The source or destination for several commands can be redirected to different I O de vices by specifying the logical unit number of the desired d...

Page 91: ...CR Load Object file MD n address count CR Memory Display MM n address data options CR Modify Memory MS address data1 data2 CR Memory Set starting at addr with datal data2 NOBR address CR Remove break...

Page 92: ...2 EXAMPLE BF 1000 1100 AA55 PHYSICAL ADDRESS 00001000 00001100 NAME BLOCK MOVE BM COMMAND SYNTAX BM address1 address2 address3 CR FUNCTION The BM command is used to move duplicate a block of memory fr...

Page 93: ...points may be set at any one time The count if specified is the number of times the address is to be encountered before the program is halted The default value is one 1 ie the program is halted as soo...

Page 94: ...hat matches after the mask is ANDed the data from memory before applying the AND mask is displayed The following data pattern size options are supported B data is byte sized default form W data is wor...

Page 95: ...read from the failing memory EXAMPLE BT 700 1FFE PHYSICAL ADDRESS 00000700 00001FFE BT 3000 4000 FAILED AT 3100 WROTE FFFE READ FFF0 NAME DATA CONVERSION DC COMMAND SYNTAX DC expression CR FUNCTION A...

Page 96: ...UMP MEMORY DU COMMAND SYNTAX DU n address1 address2 string CR FUNCTION The DUMP command enables memory data to be output to an external device in the form of an ASCII converted binary S records object...

Page 97: ...tion processing BUSERROR etc Note If breakpoints with counts are in operation the target program will not run in real time See also BR TR TT EXAMPLE Refer to command GT NAME GO DIRECT TO EXECUTE PROGR...

Page 98: ...000428 A4 00000444 A5 0000058E A6 0000058E A7 00000654 00100A 4E71 NOP GO 1000 PHYSICAL ADDRESS 00001000 AT BREAKPOINT PC 00100A SR 2700 S7 US FFEFDE77 SS 00000654 D0 00300643 D1 00000045 D2 0000067C...

Page 99: ...displays the monitor command names on the terminal EXAMPLE HE PC SR US SS D0 D1 D2 D3 D4 A5 D6 A7 A0 A1 A2 A3 A4 A5 D6 A7 R0 R1 R2 R3 R4 R5 R6 BF BM BR NOBR BS BT DC DF DU C GD GO GT HE LO M MD MM MS...

Page 100: ...Display the object file being loaded from port 2 on the terminal Default X string string is output before the load operation commences This is intended to instruct an external device to down load the...

Page 101: ...y other command terminates this feature The command can be redirected to the following devices MD Port 1 Terminal default MD1 Port 1 Terminal MD2 Port 2 Host MD3 Port 3 Printer optional See also MM MS...

Page 102: ...dress present data new data CR If new data is specified place in address display the address and contents of the next location address present data new data CR If new data is specified place in addres...

Page 103: ...ng data to non RAM locations such as hardware registers See also MD MS Several modes allow modification and verification of data data CR update location and go forward data CR update location and go b...

Page 104: ...0 000700 41 42 43 44 45 46 47 48 49 4A NAME REMOVE BREAKPOINT NOBR COMMAND SYNTAX NOBR address CR FUNCTION The NOBR command removes one or more addresses from the breakpoint table it functions as the...

Page 105: ...each have different load addresses For user convenience seven general purpose offsets R0 to R6 are provided R7 is always zero to provide a convenient means of entering an address without an offset Unl...

Page 106: ...nd or change the characteristics of the serial ports The number of stop bits and the character NULL padding may be altered EXAMPLE COMMAND FORMAT DESCRIPTION PF Display port format information Port 1...

Page 107: ...minal communicates directly with the host Note Both ports must be set to the same baud rate The transparent mode is terminated by the receipt of the exit character If it is not specified in the TM com...

Page 108: ...1000 T 2 PHYSICAL ADDRESS 00000000 PC 001002 R 2700 S7 US FFEFDE77 SS 0000067C D0 00300643 D1 00000045 D2 0000067C D3 00000000 D4 00005000 D5 00000000 D6 00000008 D7 00000041 A0 0000FFA1 A1 00005032...

Page 109: ...kpoint is encountered EXAMPLE PC 1000 TT 1008 PHYSICAL ADDRESS 00001008 PHYSICAL ADDRESS 00001000 AT BREAKPOINT PC 001008 SR 2700 S7 US FFEFDE77 SS 0000067C D0 00300643 D1 0000045 D2 0000067C D3 00000...

Page 110: ...ed an error message is displayed on the terminal string if specified is output before the verification operation commences it is intended as a means of instructing an external device to download the f...

Page 111: ...nter EXAMPLE PC Display program counter PC 00001010 A7 1300 Set address register 7 R5 5500 Set relative offset register 5 NAME MEMORY DISPLAY DISASSEMBLER MD DI COMMAND SYNTAX MD n address counts DI C...

Page 112: ...the program counter The assembler will assemble and print the new line If there is an error in the assembly instruction entered a will be printed and the entire line must be re entered To insert line...

Page 113: ...nd locations in a program The one line assembler has no knowledge of other program lines and therefore cannot make the required association between a label and a label definition located on a separate...

Page 114: ...C W directive Each statement follows a consistent source line format see also commands MD DI and MM DI For further details on source program coding and on the 68000 instruction set see the 68000 Users...

Page 115: ...of the monitor commands One or more ASCII characters enclosed by apostrophes constitute an ASCII string ASCII strings are left justified and zero filled if necessary whether stored or used as immedia...

Page 116: ...period slash dash g The asterisk indicates current location Source Code Format This section describes the functions performed by assemblers in comparison with the ROM resident assembler disassembler A...

Page 117: ...xplicitly specified a default size is taken BYTE B 8 bit WORD W 16 bit default LONG L 32 bit Several instructions do not have or do not request a data size specification Format OP SIZE Valid operation...

Page 118: ...into the PME 68 1B RAM area using the one line assembler disassembler It is entered in assembly language statements on a line by line base The source code is not saved as it is immediately converted...

Page 119: ...to request a new input For severe errors an error message is displayed and a return to the monitor prompt is performed Disassembled Program Listings A listing of the program is obtained using the Memo...

Page 120: ...ogram has been sent it can be saved on the hosts mass storage media Up loading to a host requires a program in the host to input the S records from the RS232C port and save them either in RAM or direc...

Page 121: ...ign is sent to the RADSTONE VME MDS and interpreted as command input The VERIFY command should be used to ensure that data has properly loaded VE DU1 2000 3000 CR If any differences are found they wil...

Page 122: ...ow the ACIA3 may be programmed in assembler language using a standard 68000 structured label assembler Output of One Line to the REMOTE ACIA A string is transmitted via the ACIA3 until CR 0D is detect...

Page 123: ...ONE LINE FROM ACIA3 ACIA EQU C0101 ACIA3 CSR RESET EQU 03 RESET MODE EQU 15 MODE START1 LEA L ACIA A0 GET BASE INTO A0 MOVE B RESET 0 A0 RESET MOVE B MODE 0 A0 LEA L STRNG A1 NEXT BSR B INCH CMPI B S...

Page 124: ...ONT EQU 15 A0 COUNT_GO EQU 2B A0 GO COMMAND REGISTER HOUR EQU 08 TIME AND DATE DAY EQU 01 WEEK EQU 11 MONT EQU 02 NULL EQU 00 START EQU FF START COMMAND STARTRTC LEA L RTCLOCK A0 GET BASE INTO A0 MOVE...

Page 125: ...gister DEVICE J3 6850 ACIA Host Address Mode Description 0C0041 R Status Register 0C0041 W Control Register 0C0043 R Receive Data Register 0C0043 W Transmit Data Register DEVICE J4 6850 ACIA Remote no...

Page 126: ...r PADR 0E0013 R W N Port B Data Register PBDR 0E0015 R N N Port A Alternate Register PAAR 0E0017 R N N Port B Alternate Register PBAR 0E0019 R W N N Port C Data Register PCDR 0E001B R W Y N Port Statu...

Page 127: ...of Month 0C040F R Counter Months 0C0411 R W RAM Ten Thousands of Seconds 0C0413 R W RAM Hundredths and Tenths of Seconds 0C0415 R W RAM Seconds 0C0417 R W RAM Minutes 0C0419 R W RAM Hours 0C041B R W...

Page 128: ...RESS Too big 1 in bits 24 32 or odd for W or L 1 in bit 0 Program does not recognise user s entry NOT HEX Same as IS NOT A HEX DIGIT FAILED AT WRITE READ Read or write command failure output by BT Mon...

Page 129: ...Terminal 81C14 A5 Bufbegin A6 Bufend 1 OUTPUT21 Output String to Host 81C34 A5 Bufbegin A6 Bufend 1 PORTIN1 Read String from Terminal until CR 81CA8 A5 A6 Textbegin PORTIN20 Read String from Host 81FD...

Page 130: ...s follows Frame Value Description 0D Carriage Return 0A Line Feed 00 Null 1 53 S Start of Record 2 30 39 0 9 Record Type 3 4 Byte Count 5 8 Address for 16 bit 5 10 Address for 24 bit 5 12 Address for...

Page 131: ...unt S0 Record Type S214020000000004440002014660000CB241F8044CB1 S214020010203C0000020E428110C1538066FA487AE4 S214020020001021DF0008487A001221DF000C4E750E S21402003021FC425553200030600821FC41444452C2 X...

Page 132: ...Blank Page PME68 1B Manual Page 126 Issue 5...

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