Radstone PME 68-1B, Manual

Page: 126 / 132

DEVICE: J50 68230 PIT (Parallel Interface/Timer)
Affected Affected by
55D
Address Mode By Reset Read Cycle Using
0E0001 R/W Y N Port General Control Register (PGCR)
0E0003 R/W Y N Port Service Request Register (PSRR)
0E0005 R/W Y N Port A Data Direction Register (PADDR)
0E0007 R/W Y N Port B Data Direction Register (PBDDR)
0E0009 R/W Y N Port C Data Direction Register (PCDDR)
0E000B R/W Y N Port Interrupt Vector Register (PIVR)
0E000D R/W Y N Port A Control Register (PACR)
0E000F R/W Y N Port B Control Register (PBCR)
0E0011 R/W N ** Port A Data Register (PADR)
0E0013 R/W N ** Port B Data Register (PBDR)
0E0015 R N N Port A Alternate Register (PAAR)
0E0017 R N N Port B Alternate Register (PBAR)
0E0019 R/W N N Port C Data Register (PCDR)
0E001B R/W* Y N Port Status Register (PSR)
0E0021 R/W Y N Timer Control Register (TCR)
0E0023 R/W Y N Timer Interrupt Vector Register (TIVR)
0E0027 R/W Y N Counter Preload Register High (CPRH)
0E0029 R/W N N Counter Preload Register Middle (CPRM)
0E002B R/W N N Counter Preload Register Low (CPRL)
0E002F R N N Count Register High (CNTRH)
0E0031 R N N Count Register Middle (CNTRM)
0E0033 R N N Count Register Low (CNTRL)
0E0035 R/W Y N Timer Status Register (TSR)
* A write to this register may perform a special status reset
operation.
** Mode dependent.
PME68-1B Manual
Page 120 Issue 5