RadiSys PL35Q, Product Manual, Page: 63 / 72

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POST checkpoint codes
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POST checkpoint codes
POST 80 codes
The tables that follow list the POST checkpoint codes that the system BIOS may send to I/O
port 80h during POST. They are presented in an alphabetically ascending order and are not
necessarily in order of execution.
If an error occurs at any of the listed checkpoints, the system attempts to generate beeps to
indicate where the error occurred. To hear the beeps, connect a speaker (not included) to the
speaker pin on the front panel I/O header. Beep codes are derived from the checkpoint code in
the following way:
1. The 8-bit hexadecimal checkpoint code is converted to binary, then the binary number is
divided into four 2-bit groups. For example:
Checkpoint code 20h = 00100000 = 00-10-00-00
2. Each 2-bit group is converted to a one-based number, and 1 is added to indicate the
number of beeps:
3. 00 10 00 00 = 1-3-1-1 beeps
Note: Only standard Phoenix TrustedCore BIOS POST 80 codes are listed in the tables below. If
you encounter other POST 80 codes, contact RadiSys for further assistance.
Phoenix TrustedCore BIOS checkpoint codes
Checkpoint Code Description
01h IPMI Initialization.
02h Verifies that CPU is in real mode from cold start.
03h Disables NMIs.
04h Gets CPU type from CPU registers.
06h Miscellaneous hardware initialization.
07h Disables system ROM shadow and start to execute from the flash device.
08h Initializes chipset registers to power-on defaults.
09h Sets In-POST bit in CMOS.
0Ah Completes any implementation-specific CPU initialization.
0Bh Enables L1 cache during POST.
0Ch Initializes cache(s).
0Fh Disables IDE operation.
11h Alternates register initialization.
12h Restores contents of CR0 following CPU reset
13h Resets PCI devices in early post.
14h Initializes and configures the keyboard controller.
16h Verifies ROM BIOS checksum.