
A
Connector Description
48
PCI Express x1 slot
Note:
The signals for hot plug presence detection in the table below are not supported on Q35
motherboards.
Pin #
Side B
Side A
Signal
Description
Signal
Description
1
+12V
12V power
PRSNT1# Hot plug presence detect
2
+12V
12V power
+12V
12V power
3
RSVD
Reserved
+12V
12V power
4
GND
Ground
GND
Ground
5
SMCLK
SMBus (System Management Bus)
clock
JTAG2
TCK (Test Clock), clock input for JTAG
interface
6
SMDAT
SMBus (System Management Bus)
data
JTAG3
TDI (Test Data Input)
7
GND
Ground
JTAG4
TDO (Test Data Output)
8
+3.3V
3.3V power
JTAG5
TMS (Test Mode Select)
9
JTAG1
TRST# (Test Reset) resets the JTAG
interface
+3.3V
3.3V power
10
3.3Vaux
3.3V auxiliary power
+3.3V
3.3V power
11
WAKE#
Signal for link reactivation
PERST#
fundamental reset
Mechanical Key
12
RSVD
Reserved
GND
Ground
13
GND
Ground
Reference clock (differential pair)
14
PETp0
Transmitter differential pair Lane 0
REFCLK-
Reference clock (differential pair)
15
PETn0
Transmitter differential pair Lane 0
GND
Ground
16
GND
Ground
PERp0
Receiver differential pair Lane 0
17
PRSNT2# Hot plug presence detect
PERn0
Receiver differential pair Lane 0
18
GND
Ground
GND
Ground
Summary of Contents for PL35Q
Page 6: ...6 ...
Page 8: ...8 ...
Page 20: ...2 Product Specification 20 ...
Page 38: ...3 Hardware Reference 38 ...
Page 58: ...A Connector Description 58 ...
Page 72: ...C 72 ...