RadiSys EPC-8A, Hardware Reference Manual

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EPC-8A Hardware Reference
42
Passing VME Interrupts and Events to the CPU
The diagram below shows how VME interrupts and VME events are generated and passed
to the CPU:
Interrupt-causing signals are visible in two state registers. Most of these are unlatched,
meaning that a read of the state register shows the actual state of the signals at the instant
of the read. The exceptions are (1) BERR, which is a “sticky” bit, meaning that the bit
signifies whether BERR had ever been asserted (the SBER register bit), and (2) RESET,
another sticky bit. The convention used is that a 0 bit signifies an asserted (interrupting)
state.
The primary purpose of the state registers is to let the interrupt handler software determine
which interrupts and events generated the IRQ10 interrupt to the processor. The state
registers can also be read by non-interrupt-handler software to poll for the state of these
signals.
The enable registers allow one to mask selectively these 14 states. A 0 state bit and a
corresponding 1 enable bit causes the PC architecture IRQ10 interrupt to be asserted.
RRDY
WRDY
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
SYSFAIL
BERR (sticky)
ACFAIL
WDT
SIGNAL FIFO
RESET (sticky)
PC
architecture
IRQ10
VME
interrupt
enable
register
VME
event
enable
register
VME
interrupt
enable
register
VME
event
enable
register
Figure 4-5. Passing VME interrupts and events to the CPU