LWORD addr; /* 32-bit A32 address */
BYTE data;
BYTE far * wptr;
outp(0x8150,(WORD)(addr >> 24); /* A31-A24 */
outp(0x8151,2 | (((addr << 8) >> 30) << 6));
/* A23-A22 and address modifier for A32 supervisory data access */
outp(0x8130,(WORD)((addr << 10) >> 24); /* A21-A14 */
wptr = (BYTE far *) (0xE00 (addr & 0X00003FFFL));
*wptr = data; /* Write through window */
The success of the access can be checked either by enabling .i.BERR; as an
interrupt or by looking at the BERR bit in the event state register after each
access. Since writes are pipelined, software that looks at the BERR bit should
first wait until the BSAM bit is set..i.pipelined write;.i.VMEbus write;
It is recommended that rather than performing accesses in this low-level
hardware dependent form, the .i.Bus Manager; component of the EPConnect software
package be used instead.
The following summarizes the source of the VMEbus address lines for accesses
through the E page.
.i.A32;
31 24 23 22 21 14 13 0
From From From From
port port port 386 address
8150 8151 8130/2/4/6 bits 13-0
.i.A24;
23 22 21 14 13 0
From From From
port port 386 address
8151 8130/2/4/6 bits 13-0
.i.A16;
15 14 13 0
From From
port 386 address
813x bits 13-0
Direct VMEbus Accesses
.i.data-transfer bus accesses;As described at the beginning of the chapter, an
alternate way to perform .i.VMEbus accesses;, providing that one is in a 32-bit
operating-system environment, is performing reads and writes at 386 addresses
between 02000000h and FEFFFFFFh. These are directly mapped to the data-transfer
bus with the same address, with an .i.address modifier; specifying .i.A32;
supervisory data, and with .i.little endian; byte order..
Byte Ordering
.i.byte ordering;There are two fundamentally different ways of storing numerical
values in byte locations in memory:
ù
.i.Little endian;, characteristic of Intel microprocessors, where the
least-significant data byte is stored in the lowest byte address
ù
.i.Big endian;, characteristic of Motorola microprocessors and the VMEbus
environment in general, where the most-significant data byte is stored in the
lowest byte address.
To understand the difference and the potential problems, assume an Intel
processor and a Motorola processor coexist in a shared memory environment. If
the Motorola processor stored the 16-bit value 0102h in memory and the Intel
processor fetched it, the Intel processor would interpret its numerical value as
0201h. If the Intel processor stored the 32-bit value 01020304h, the Motorola
processor would fetch it as the number 04030201h.
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