Similar to the interrupt state register, this register defines additional
conditions that may result in an .i.IRQ10 interrupt;. If the bit is 0, the
condition is present.
SIGR .i.Signal register FIFO; is not empty.
WDT
The EPC-2 .i.watchdog timer; period has expired.
ACFA VXIbus .i.ACFAIL; is asserted.
BERR An access from the EPC-2 to the VXIbus was terminated with a .i.BERR;
(.i.bus error;).
SYSF VXIbus .i.SYSFAIL; is asserted.
.i.VME Event Enable Register; (.i.BEE;)
DSOR VWR 1 SIGR WDT ACFA BERR SYSF
8155
The low-order five bits are a mask of the interrupt conditions in the event
state register. A 1 denotes that the corresponding event is enabled as an
interrupt. If any bit in this register is a 1 and the corresponding bit in the
event state register is a 0, the EPC-2 .i.IRQ10 interrupt; is asserted.
Software may then examine the interrupt and event state registers to determine
the cause.
The following two bits are read-only state bits:
DSOR Clear whenever either of the VXI DS0/DS1 .i.data strobes; is asserted.
DSOR=0 thus indicates a data transfer in progress.
VWR
When DSOR is 0, VWR=0 indicates that the data transfer is a write
operation.
.i.TTL Trigger Sample Register; (.i.BTTS;)
TTS7 TTS6 TTS5 TTS4 TTS3 TTS2 TTS1 TTS0
8156
This read-only register contains the state of the eight TTL trigger lines on the
VXI J2 backplane. A 1 denotes an asserted trigger. Note that this register
does not necessarily match the value in the TTL drive register because of the
open-collector nature of the trigger lines.
.i.MODID / Interrupt Generator Register; (.i.BMOL;)
MO04 MO03 MO02 MO01 MO00 INTERRUPT-OUT
8158
This register serves two purposes: an extension of the MODID bits in the BMOH
register, and VXI .i.interrupt generation;.
If the three low-order bits are not 000, one of the seven VXI interrupt lines is
asserted by the EPC-2. The line is the decoded value of these three bits (e.g.,
001 denotes IRQ1, 111 denotes IRQ7). If and when an .i.interrupt acknowledge;
cycle is sent to the EPC-2, the INTERRUPT-OUT bits are cleared. Software can
also deassert an asserted interrupt by clearing these bits at any time. A reset
of the EPC-2 or setting bit RSTP in the .i.VSC; register clears the INTERRUPT-
OUT bits.
.i.MODID Upper Register; (.i.BMOH;)
MO12 MO11 MO10 MO09 MO08 MO07 MO06 MO05
8159
This register and BMOL drive and sample the LBUSA .i.local bus; signals on the
VXI P2 connector. When the EPC-2 is installed in .i.slot 0;, these signals are
the MODID signals on the VXI backplane. The bits named MO00-MO12 are associated
with signals MODID00-MODID12.
When a write occurs to BMOH, the EPC-2 drives the MODID signals on the back-
plane. A read of BMOH terminates the driving of the signals; the value returned
from this "driver-terminating" read is not specified and should not be used.
All other reads of BMOH and BMOL sample the MODID signals from the backplane. A
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