
1260-100/101 Adapt-a-Switch Carrier Module User Manual
B-4
The 13 address bits are clocked into U5 and U6, as when writing. After sending the address, the
Option-01T drives the HLBUS_A/D low, indicating that it is ready for data. The plug-in containing
the addressed device begins shifting serial data onto HLBUS_DATAOUT. There are eight data
bits, with the most-significant bit sent first.
The signal HLBUS_STROBE is used only when writing, not when reading. During reading, it
remains at logic 0.
Power Distribution
The Bridge PCB co5V, +12V, and +24V power from the VXIbus backplane to the 1260-100
backplane to add to the current provided by the Mezzanine.
The bridge also filters power in the same manner as the Mezzanine.
PLD Programming Connector
J5 is a 10-pin header that is connected to the PLD (U1). It uses the JTAG interface to allow in-
system programming of the PLD during upgrades or troubleshooting.
Summary of Contents for 1260-100
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