RabbitCore RCM2200, User Manual

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A– 6 RabbitCore RCM2200 Specifications RabbitCore RCM2200
Figure A–3 shows a typical timing diagram for the Rabbit 2000 microprocessor external memory read and
write cycles.
T
adr
is the time required for the address output to reach 0.8 V. This time depends on the bus loading. T
setup
is
the data setup time relative to the clock. Tsetup is specified from 30%/70% of the V
DD
voltage level.
Figure A–3:
Memory Read and Write Cycles
Tadr
Tadr
External I/O Read (no extra wait states)
Thold
valid
CLK
A[15:0]
D[7:0]
valid
Tsetup
Thold
External I/O Write (no extra wait states)
CLK
A[15:0]
D[7:0]
/CSx
/OEx
/CSx
/WEx
valid
T1 Tw
T1
Tw T2
valid
T2
valid
/IOCSx
/IORD
/BUFEN
valid
/IOCSx
/IOWR
/BUFEN