Smart LTE Module Series
SC650T Hardware Design
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Table 16: Pin Definition of I2S Interface
3.16. SPI Interfaces
SC650T provides two SPI interfaces which only support master mode. The two interfaces are typically
applied for fingerprint identification.
Table 17: Pin Definition of SPI Interfaces
Pin Name
Pin No
I/O Description
Comment
GPIO_22
58
DO
Chip selection signal of SPI interface
Can be multiplexed
into SPI_CS.
GPIO_23
59
DO
Clock signal of SPI interface
Can be multiplexed
into SPI_CLK.
UART6_TXD
60
DO
Master out slave in of SPI interface
Can be multiplexed
into SPI_MOSI.
UART6_RXD
61
DI
Master in salve out of SPI interface
Can be multiplexed
into SPI_MISO.
FP_SPI_CS0
203
DO
Chip selection signal of SPI interface
Used for fingerprint
identification by
default. Can be
FP_SPI_CS1
232
DO
Chip selection signal of SPI interface
Pin Name
Pin No
I/O Description
Comment
I2S_MCLK
234
DO
Master clock signal of
I2S interface
I2S_MCLK
I2S_1_SCK
212
DO
Clock signal of I2S
interface
I2S_1_SCK
I2S_1_WS
156
DO
Channel selection signal
of I2S interface
I2S_1_WS
I2S_1_D0
154
IO
Data0 signal of I2S
interface
I2S_1_D0
I2S_1_D1
155
IO
Data1 signal of I2S
interface
I2S_1_D1
I2S_1_D2
213
IO
Data2 signal of I2S
interface
I2S_1_D2
I2S_1_D3
214
IO
Data3 signal of I2S
interface
I2S_1_D3
