Smart LTE Module Series
SC650T Hardware Design
SC650T_Hardware_Design 55 / 131
CMD, CLK, DATA0, DATA1, DATA2 and DATA3 are all high speed signal lines. In PCB design, please
control the characteristic impedance of them as 50
Ω, and do not cross them with other traces. It is
recommended to route the trace on the inner layer of PCB, and keep the same trace length for CLK, CMD,
DATA0, DATA1, DATA2 and DATA3. CLK additionally needs ground shielding.
Layout guidelines:
Control impedance as 5
0Ω±10%, and ground shielding is required.
The total trace length difference between CLK and other signal line traces should not exceed 1mm.
Table 13: SD Card Signal Trace Length Inside the Module
Pin No.
Signal
Length (mm)
Comment
70
SD_CLK
30.44
69
SD_CMD
31.60
68
SD_DATA0
31.50
67
SD_DATA1
30.96
66
SD_DATA2
32.70
65
SD_DATA3
31.62
3.13. GPIO Interfaces
SC650T has abundant GPIO interfaces with power domain of 1.8V. The pin definition is listed below.
Table 14: Pin Definition of GPIO Interfaces
Pin Name
Pin No.
GPIO
Default Status
Comment
GPIO_0
248
GPIO_0
B-PD:nppukp
1)
GPIO_1
247
GPIO_1
B-PD:nppukp
Wakeup
2)
GPIO_2
201
GPIO_2
B-PD:nppukp
GPIO_3
200
GPIO_3
B-PD:nppukp
