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Quectel QuecOpen AG521R-NA, Hardware Design

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Automotive  Module  Series 

                                                                                                  AG521R-NA  QuecOpen

 

Hardware  Design

 

AG521R-NA_QuecOpen_Hardware_Design                                                                                      61  / 92 

 
 

 

R13

R14

R15

R16

RGMII_VDDO

R1 0R

R2 0R

R3 0R

R4 0R

R5 0R

R6 0R

R7 0R

R8 0R

R9 0R

R10 0R

R11 0R

R12 0R

RGMII_PWR_EN

RGMII_PWR_IN

RGMII_VDDO

RGMII_RX_0

RGMII_RX_1

RGMII_RX_2

RGMII_RX_3

RGMII_CTL_RX

RGMII_CK_RX

RGMII_TX_0

RGMII_TX_1

RGMII_TX_2

RGMII_TX_3

RGMII_CTL_TX

RGMII_CK_TX

RGMII_PWR_EN

Module

RGMII_RST

RGMII_INT

RGMII_MD_CLK

RGMII_MD_IO

RGMII_PWR_IN

MDIO

INTN

RESETN

Ethernet PHY

MDC

RXD0

RXD1

RXD2

RXD3

RXC

RCLK

TXD0

TXD1

TXD2

TXD3

RCLK

RXC

VDDO

 

Figure 28: Reference Circuit of RGMII Interface with PHY Application 

 
In order to enhance the reliability and availability of customers’ application, please follow the criteria below in the 

Ethernet PHY circuit design:   

 

⚫

 

The I/O voltage of RGMII matches with that of PHY. 

⚫

 

The voltage of RGMII_INT and RGMII_RST matches with the I/O voltage of PHY. 

⚫

 

The typical power consumption of RGMII_PER_IN is 300 mA @ 1.8 V. 

⚫

 

Keep RGMII data and control signals away from RF and VBAT traces. 

⚫

 

Assure impedance of RGMII signals trace is 50 Ω ±20%. 

⚫

 

The length difference among CK_TX, CTL_TX and TX_[0-3] is less than 2 mm. 

⚫

 

The length difference among CK_RX, CTL_RX and RX_[0-3] is less than 2 mm. 

⚫

 

TX bus (CK_TX to CTL_TX/TX_[0-3]) spacing or RX bus (CK_RX to CTL_RX/RX_[0-3]) spacing is larger 

than two times of the line width. 

⚫

 

Spacing between TX bus and RX bus is larger than 2.5 times of line width. 

⚫

 

Spacing to all other signals is larger than three times of line width. 

⚫

 

Resistors R7–R12 should be placed near the module. Resistor R1–R6 should be placed near the Ethernet PHY. 

Summary of Contents for QuecOpen AG521R-NA

Page 1: ...AG521R NA QuecOpen Hardware Design Automotive Module Series Version 1 0 0 Date 2021 01 26 Status Preliminary www quectel com ...

Page 2: ...out prior notice Disclaimer While Quectel has made efforts to ensure that the functions and features under development are free from errors it is possible that these functions and features could contain errors inaccuracies and omissions Unless otherwise provided by valid agreement Quectel makes no warranties of any kind implied or express with respect to the use of features and functions under dev...

Page 3: ...tel Wireless Solutions Co Ltd Transmitting reproducing disseminating and editing this document as well as using the content without permission are forbidden Offenders will be held liable for payment of damages All rights are reserved in the event of a patent grant or registration of a utility model or design Copyright Quectel Wireless Solutions Co Ltd 2020 All rights reserved ...

Page 4: ...dware Design AG521R NA_QuecOpen_Hardware_Design 3 104 About the Document Revision History Version Date Author Description 2020 04 04 Leon HUANG Alex ZHANG Evan SHEN Creation of the document 1 0 2021 01 26 Charlie Bao Jacky CHEN Evan SHEN Preliminary ...

Page 5: ...3 5 1 1 USB Application with USB Remote Wakeup Function 38 3 5 1 2 USB Application without USB Remote Wakeup Function 38 3 5 1 3 USB Application without USB Suspend Function 39 3 5 2 Airplane Mode 40 3 6 Power Supply 40 3 6 1 Power Supply Pins 40 3 6 2 Decrease Voltage Drop 41 3 6 3 Reference Design for Power Supply 42 3 6 4 Monitor the Power Supply 42 3 7 Power on and off Scenarios 42 3 7 1 Turn ...

Page 6: ...RF Layout 70 4 2 Antenna Installation 72 4 2 1 Antenna Requirements 72 4 2 2 Recommended RF Connector for Antenna Installation 72 5 Reliability Radio and Electrical Characteristics 74 5 1 Absolute Maximum Ratings 74 5 2 Power Supply Ratings 74 5 3 Operation and Storage Temperatures 75 5 4 Current Consumption 75 5 5 RF Output Power 76 5 6 RF Receiving Sensitivity 77 5 7 Electrostatic Discharge 78 5...

Page 7: ...rface 55 Table 19 Pin Definition of SDIO Interface 55 Table 20 Pin Definition of SPI Interfaces 58 Table 21 Parameters of SPI Interface Timing 58 Table 22 Pin Definition of RGMII Interface 59 Table 23 Pin Definition of WLAN and BT Interfaces 62 Table 24 Pin Definition of ADC Interfaces 65 Table 25 Characteristic of ADC Interface 65 Table 26 Pin Definition of USB_BOOT Interface 66 Table 27 Pin Defi...

Page 8: ...Automotive Module Series AG521R NA QuecOpen Hardware Design AG521R NA_QuecOpen_Hardware_Design 7 104 Table 42 GPRS Multi slot Classes 92 Table 43 EDGE Modulation and Coding Schemes 92 ...

Page 9: ...nnector 49 Figure 20 Reference Circuit of USB 2 0 Application 51 Figure 21 Reference Circuit of USB 3 0 Application 51 Figure 22 Reference Circuit with Translator Chip 53 Figure 23 Reference Circuit with Transistor Circuit 54 Figure 24 Reference Circuit of I2S and I2C Application with Audio Codec 55 Figure 25 Reference Design of SDIO Interface for eMMC Application 57 Figure 26 SPI Timing 58 Figure...

Page 10: ...are Design AG521R NA_QuecOpen_Hardware_Design 9 104 Figure 42 Top View of the Module 84 Figure 43 Bottom View of the Module 84 Figure 44 Recommended Reflow Soldering Thermal Profile 86 Figure 45 Tape Specifications 88 Figure 46 Reel Specifications 88 ...

Page 11: ...al and mechanical details as well as other related information of the module With the application notes and user guides provided separately you can easily use the module to design and set up mobile applications FCC Certification Requirements According to the definition of mobile and fixed device is described in Part 2 1091 b this device is a mobile device And the following conditions must be met 1...

Page 12: ...t paragraph For a host using a certified modular with a standard fixed label if 1 the module s FCC ID is not visible when installed in the host or 2 if the host is marketed so that end users do not have straightforward commonly used methods for access to remove the module so that the FCC ID of the module is visible then an additional permanent label referring to the enclosed module Contains Transm...

Page 13: ...nt Dé claration sur l exposition aux rayonnements RF L autre utilisépour l é metteur doit ê tre installépour fournir une distance de sé paration d au moins 20 cm de toutes les personnes et ne doit pas ê tre colocaliséou fonctionner conjointement avec une autre antenne ou un autre é metteur The host product shall be properly labeled to identify the modules within the host product The Innovation Sci...

Page 14: ...are facilities Cellular terminals or mobiles operating over radio signal and cellular network cannot be guaranteed to connect in certain conditions such as when the mobile bill is unpaid or the U SIM card is invalid When emergent help is needed in such conditions use emergency call if the device supports it In order to make or receive a call the cellular terminal or mobile must be switched on in a...

Page 15: ...eered to meet the demanding requirements in automotive applications and other harsh operating conditions the module offers a premium solution for high performance automotive and intelligent transportation system ITS applications such as fleet management onboard vehicle telematics in car entertainment systems emergency calling and roadside assistance With a compact profile of 38 0 mm 42 0 mm 2 65 m...

Page 16: ...upport TCP UDP PPP FTP HTTP NTP PING QMI HTTPS MMS FTPS SSL protocols Support PAP and CHAP used for PPP connections SMS Text and PDU modes Point to point MO and MT SMS cell broadcast SMS storage ME by default U SIM Interfaces Support USIM SIM card 1 8 3 0 V Audio Features Provide one digital audio interface I2S interface LTE AMR AMR WB Support echo cancellation and noise suppression I2S Interface ...

Page 17: ...t supported Used for codec configuration by default RGMII Interface Support 10 100 1000 Mbps Wireless Connectivity Interface PCIe Gen2 interface for WLAN UART PCM interfaces for Bluetooth Rx diversity Support LTE Rx diversity Antenna Interfaces Main antenna interface ANT_MAIN Rx diversity antenna interface ANT_DIV GNSS antenna interface ANT_GNSS Physical Characteristics Dimensions 38 0 0 2 mm 42 0...

Page 18: ...level the module will meet 3GPP specifications again 3 3 Within eCall temperature range the emergency call function must be functional until the module is broken When the ambient temperature is between 75 C and 90 C and the module temperature has reached the threshold value the module will trigger protective measures such as reduce power decrease throughput and unregister the device to ensure the ...

Page 19: ...X_TRX1 PCM PCIe USB2 0 3 0 SPI UART 3 I2C SDIO RGMII U SIM GPIOs I2S VDD_EXT TX RX Blocks ANT_DIV ANT_MAIN VBAT_RF APT ANT_MIMO3 ANT_MIMO4 TX PRX DRX GNSS MIPI GRFC PRX DRX Figure 1 Functional Diagram for AG521R NA QuecOpen 2 4 Evaluation Board To help you develop applications conveniently with the module Quectel supplies the evaluation board EVB USB data cables a pair of earphones antennas and ot...

Page 20: ... 400 LGA pins that can be connected to cellular application platforms Module interfaces are described in detail in the following sub chapters Power supply U SIM interfaces USB 2 0 3 0 interface UART interfaces I2S and I2C interfaces SDIO interface SPI interfaces RGMII interface WLAN and BT interfaces ADC interfaces USB_BOOT interface GPIO interfaces means under development NOTE ...

Page 21: ...X 22 RGMII_TX_1 23 RGMII_TX_2 24 RGMII_CK_TX 25 RGMII_TX_3 GND 26 GND 27 RGMII_PWR_EN 28 RGMII_PWR_IN 29 RGMII_INT 30 PCIE_WAKE 31 RGMII_RST RGMII_RST 32 PCIE_RX_M 33 GND 34 PCIE_RX_P 35 RESERVED 36 PCIE_CLKREQ 37 RESERVED 38 PCIE_REFCLK_M 39 PCIE_RST 40 PCIE_REFCLK_M 41 RESERVED 42 GND 43 RESERVED 44 PCIE_TX_M 45 EMMC_PWR_EN 46 PCIE_TX_P 47 SDC1_CLK 47 SDC1_CLK 48 SDC1_CMD 49 SDC1_DATA_0 50 SDC1_...

Page 22: ...n The following tables show the pin definition of the module and the alternate functions of multiplexing pins Table 3 I O Parameters Definition Type Description AI Analog input AO Analog output B Bidirectional digital with CMOS input DI Digital input DO Digital output H High level IO Bidirectional L Low level OD Open drain PD Pull down PI Power input PO Power output PU Pull up R Slew rate limited ...

Page 23: ...eep it open VDD_WIFI_V M 276 PO Power supply for Wi Fi Vnorm 1 35 V If unused keep it open VDD_WIFI_VH 277 PO Power supply for Wi Fi Vnorm 1 95 V If unused keep it open GND 12 18 26 33 42 86 92 98 115 117 118 120 121 124 131 133 135 137 138 140 141 144 151 153 155 156 158 159 160 162 164 165 167 168 171 174 176 177 180 182 183 185 186 189 191 192 194 195 198 199 201 203 206 208 209 211 212 215 217...

Page 24: ...0 4 V VOHmin 2 28 V If unused keep it open USIM1_CLK 253 DO U SIM1 card clock For 1 8 V U SIM VOLmax 0 4 V VOHmin 1 44 V For 3 0 V U SIM VOLmax 0 4 V VOHmin 2 28 V If unused keep it open USIM1_RST 250 DO U SIM1 card reset For 1 8 V U SIM VOLmax 0 4 V VOHmin 1 44 V For 3 0 V U SIM VOLmax 0 4 V VOHmin 2 28 V If unused keep it open USIM1_DET 255 DI U SIM1 card hot plug detect VILmin 0 3 V VILmax 0 63...

Page 25: ...2 28 V If unused keep it open USIM2_RST 260 DO U SIM2 card reset For 1 8 V U SIM VOLmax 0 4 V VOHmin 1 44 V For 3 0 V U SIM VOLmax 0 4 V VOHmin 2 28 V If unused keep it open USIM2_DET 258 DI U SIM2 card hot plug detect VILmin 0 3 V VILmax 0 63 V VIHmin 1 17 V VIHmax 2 1 V 1 8 V power domain If unused keep it open USB Interfaces Pin Name Pin No I O Description DC Characteristics Comment USB_VBUS 84...

Page 26: ...1 V VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain If unused keep them open GPIO2 101 IO General purpose input output GPIO3 102 IO General purpose input output GPIO4 104 IO General purpose input output GPIO5 116 IO General purpose input output GPIO6 243 IO General purpose input output GPIO7 246 IO General purpose input output GPIO8 249 DO General purpose output VILmin TBD VILmax 0 63 V VIHmin 0 9 ...

Page 27: ...V VIHmin 1 17 V VIHmax 2 1 V BT_UART_RTS 61 DI BT UART request to send VILmin 0 3 V VILmax 0 63 V VIHmin 1 17 V VIHmax 2 1 V BT_UART_CTS 62 DO BT UART clear to send VOLmax 0 45 V VOHmin 1 35 V Debug UART Interface Pin Name Pin No I O Description DC Characteristics Comment DBG_RXD 110 DI Debug UART receive VILmin 0 3 V VILmax 0 63 V VIHmin 1 17 V VIHmax 2 1 V 1 8 V power domain DBG_TXD 107 DO Debug...

Page 28: ...ax 2 1 V I2S_SCK 262 DO I2S clock VOLmax 0 45 V VOHmin 1 35 V I2S_DIN 263 DI I2S data in VILmin 0 3 V VILmax 0 63 V VIHmin 1 17 V VIHmax 2 1 V I2S_DOUT 261 DO I2S data out VOLmax 0 45 V VOHmin 1 35 V PCM Interface Pin Name Pin No I O Description DC Characteristics Comment PCM_SYNC 73 IO PCM data frame sync VOLmax 0 45 V VOHmin 1 35 V VILmin 0 3 V VILmax 0 63 V VIHmin 1 17 V VIHmax 2 1 V 1 8 V powe...

Page 29: ...k request VOLmax 0 45 V VOHmin 1 35 V VILmin 0 3 V VILmax 0 63 V VIHmin 1 17 V VIHmax 2 1 V 1 8 V power domain If unused keep them open PCIE_RST 39 DO PCIe reset VOLmax 0 45 V VOHmin 1 35 V PCIE_WAKE 30 DI PCIe wakeup VILmin 0 3 V VILmax 0 63 V VIHmin 1 17 V VIHmax 2 1 V RGMII Interface Pin Name Pin No I O Description DC Characteristics Comment RGMII_MD_IO 10 IO RGMII MDIO management data Power do...

Page 30: ...n RGMII_PWR_IN 28 PI Power input for internal RGMII circuit 1 8 2 5 V power supply input If RGMII is not be used connect it to VDD_EXT RGMII_INT 29 DI RGMII PHY interrupt output VILmin 0 3 V VILmax 0 63 V VIHmin 1 17 V VIHmax 2 1 V 1 8 V power domain If unused keep them open RGMII_RST 31 DO Reset output for RGMII PHY VOLmax 0 45 V VOHmin 1 35 V SDIO Interface for eMMC by default Pin Name Pin No I ...

Page 31: ... open EMMC_PWR_E N 45 DO eMMC power supply enable control VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain If unused keep it open SPI Interfaces Pin Name Pin No I O Description DC Characteristics Comment SPI1_CLK 216 DO SPI1 clock VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain If unused keep them open Can be configured into GPIOs SPI1_CS 213 DO SPI1 chip select VOLmax 0 45 V VOHmin 1 35 V SPI1_MISO ...

Page 32: ...pt 2 VILmin 0 3 V VILmax 0 63 V VIHmin 1 17 V VIHmax 2 1 V IMU_PWR_EN 181 DO IMU power enable control VOLmax 0 45 V VOHmin 1 35 V WLAN Interface Pin Name Pin No I O Description DC Characteristics Comment WLAN_PWR_ EN2 225 DO WLAN power supply enable control 2 VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain If unused keep them open 1 8 V power domain If unused keep them open WLAN_PWR_ EN1 222 DO WLA...

Page 33: ... O Description DC Characteristics Comment ANT_MAIN 143 AI AO Main antenna interface 50 Ω impedance ANT_DIV 170 AI Diversity antenna interface RESERVED Pins Pin Name Pin No Comment RESERVED 1 6 9 35 37 41 43 64 65 82 89 94 96 97 99 103 105 106 108 113 119 122 123 132 136 139 142 152 154 157 161 163 166 175 178 179 184 188 190 193 196 197 200 204 205 207 214 223 224 226 227 229 252 264 266 275 278 3...

Page 34: ...E PCIe BS PD L Y 1 8 V 36 PCIE_CLKREQ BS PD L Y 1 8 V 39 PCIE_RST BS PD L Y 1 8 V 45 EMMC_PWR_EN SDIO BS PD L Y 1 8 V 53 SDC1_DATA_4 GPIO_92 BSH PD L N 1 8 V 54 EMMC_RST BS PD L Y 1 8 V 55 SDC1_DATA_5 GPIO_93 BSH PD L Y 1 8 V 56 SDC1_DATA_6 GPIO_94 BSH PD L Y 1 8 V 58 SDC1_DATA_7 GPIO_95 BSH PD L Y 1 8 V 59 BT_UART_TXD UART GPIO_63 BS PD L N 1 8 V 61 BT_UART_RTS GPIO_65 BS PD L Y 1 8 V 62 BT_UART_...

Page 35: ... I2S_DIN GPIO_13 BS PD L Y 1 8 V 78 PCM_OUT I2S_DOUT GPIO_14 BS PD L Y 1 8 V 77 CDC_RST I2S GPIO_86 BS PD L Y 1 8 V 81 I2S_MCLK GPIO_62 BS PD L N 1 8 V 261 I2S_DOUT PCM_OUT GPIO_18 BS PD L Y 1 8 V 262 I2S_SCK PCM_CLK GPIO_19 BS PD L Y 1 8 V 263 I2S_DIN PCM_IN GPIO_17 BS PD L Y 1 8 V 265 I2S_WS PCM_SYNC GPIO_16 BS PD L Y 1 8 V 79 I2C1_SCL I2C BSR PD L Y 1 8 V 80 I2C1_SDA BSR PD L Y 1 8 V 250 USIM1_...

Page 36: ...S PD L Y 1 8 V 219 SPI1_MISO GPIO_73 BS PD L N 1 8 V 66 BT_EN Others BS PD L Y 1 8 V 83 USB_BOOT BS PD L N 1 8 V 95 DR_SYNC BS PD L Y 1 8 V 169 IMU_INT1 GPIO_88 BS PD L Y 1 8 V 181 IMU_PWR_EN GPIO_91 BS PD L N 1 8 V 187 IMU_INT2 GPIO_82 BS PD L Y 1 8 V 222 WLAN_PWR_EN1 BS PD L Y 1 8 V 225 WLAN_PWR_EN2 BS PD L Y 1 8 V 228 WLAN_EN BS PD L Y 1 8 V 100 GPIO1 GPIO BS PD L Y 1 8 V 101 GPIO2 BS PD L Y 1 ...

Page 37: ...n 2 1 See Table 4 for more details about the symbol description 3 2 If the GPIOs without interrupt function are configured as interrupt GPIOs power consumption of the module will be increased Y means interrupt function supported N means interrupt function not supported 4 Pins 69 and 83 cannot be pulled up before power up 246 GPIO7 BS PD L Y 1 8 V 249 GPIO8 L N 1 8 V NOTES ...

Page 38: ...ill be invalid Airplane Mode AT CFUN 4 can set the module into airplane mode In this case RF function will be invalid Sleep Mode In this mode the current consumption of the module will be reduced to the minimal level During this mode the module can still receive paging message SMS voice call and TCP UDP data from the network normally Power Down Mode In this mode the power management unit shuts dow...

Page 39: ...able 5 are under non wakeup status The host s USB bus which is connected with the module s USB interface enters suspended state The following figure shows the connection between the module and the host USB Interface VDD USB Interface Module Host GND GND USB_VBUS Figure 4 Sleep Mode Application with USB Remote Wakeup Sending data to the module through USB will wake up the module When the module has...

Page 40: ...plication without USB Remote Wakeup Sending data to the module through USB will wake up the module When the module has URC to report the module s GPIO signal can be used to wake up the host 3 5 1 3 USB Application without USB Suspend Function If the host does not support USB suspend function USB_VBUS should be connected with an external control circuit to set the module to sleep mode Use sleep API...

Page 41: ... SIM and RF functions are disabled AT CFUN 1 Full functionality mode by default AT CFUN 4 Airplane mode RF function is disabled 3 6 Power Supply 3 6 1 Power Supply Pins The module provides seven VBAT pins for connection with an external power supply Three VBAT_BB pins for module s baseband part Four VBAT_RF pins for module s RF part Table 7 VBAT and GND Pins Pin Name Pin No Description Min Typ Max...

Page 42: ... reserved due to its low ESR It is recommended to use three ceramic capacitors 100 nF 33 pF 10 pF for composing the MLCC array and place these capacitors close to VBAT pins DC_3V8 from an external application has to be a single voltage source and can be expanded to two sub paths with star structure The width of VBAT_BB trace should be no less than 1 mm The width of VBAT_RF trace should be no less ...

Page 43: ...ce The designed output for the power supply is about 3 8 V and the maximum rated current is 5 A 2 4 1 3 6 7 8 182K NM 100K 10 pF 100 pF 100 nF 10 µF 470 µF 100 nF 100 nF DC_IN 100 µ H 5V_EN 100 nF BOOT VIN EN RT CLK SW GND COMP FB GND TPS54560 Q1 7 2 µH 9 5 220 µF 1 µF 10 nF 4 3K 4 7 nF 4 7 pF 75k 20k DC_3V8 Figure 9 12 24 V Power Supply System Reference Design To avoid damaging internal flash do ...

Page 44: ... control the PWRKEY A simple reference circuit is illustrated in the following figure Turn on pulse PWRKEY 4 7K 47K 500 ms Figure 10 Turn on the Module Using Driving Circuit Another way to control the PWRKEY is using a button directly When pressing the key electrostatic strike may generate from the finger Therefore a TVS component is indispensable to be placed nearby the button for ESD protection ...

Page 45: ...ast 30 ms before pulling down PWRKEY pin 2 It is recommended to use an external OD OC circuit to control the PWRKEY pin 3 7 2 Turn on Module with PON_1 Table 9 PON_1 Pin Description Pin Name Pin No Description Comment PON_1 248 Driving it high will turn on the module automatically Valid trigger range 0 78 V 1 89 V When the module is powered off drive PON_1 high for at least 500 ms will turn on the...

Page 46: ...ng methods can be used to turn off the module Normal power down procedure Turn off the module using the PWRKEY pin Normal power down procedure Turn off the module using API interface 3 7 3 1 Turn off Module Using PWRKEY Driving PWRKEY low for at least 2 s the module will execute power down procedure after PWRKEY is released The power off scenario is illustrated in the following figure VBAT PWRKEY ...

Page 47: ... turn off module with API please keep PWRKEY at high level after the execution of power off command Otherwise the module will be turned on again after successfully turn off 3 8 Reset the Module RESET can be used to reset the module The module can be reset by driving RESET low for at least 370 ms As the RESET pin is sensitive to interference the routing trace is recommended to be as short as possib...

Page 48: ...620 ms Figure 15 Reference Circuit of RESET by Using Driving Circuit RESET S2 Close to S2 TVS Figure 16 Reference Circuit of RESET by Using Button The reset scenario is illustrated in the following figure VIL 0 63 V VIH 1 17 V VBAT 370 ms Resetting Module Status Running RESET Restart 620 ms Figure 17 Timing of Resetting Module NOTE ...

Page 49: ... disabled by default and can be enabled by AT QSIMDET See document 3 for more details of the command The following figure shows a reference design for U SIM interface with an 8 pin U SIM card connector Pin Name Pin No I O Description Comment USIM1_VDD 251 PO U SIM1 card power supply Either 1 8 V or 3 0 V is supported by the module automatically USIM1_DATA 254 IO U SIM1 card data USIM1_CLK 253 DO U...

Page 50: ...ATA 22R 22R 22R 100 nF U SIM Card Connector GND VCC RST CLK IO VPP GND 10K USIM_VDD 33 pF 33 pF 33 pF Figure 19 Reference Circuit of U SIM Interface with a 6 Pin U SIM Card Connector To enhance the reliability and availability of the U SIM card follow the criteria below in the U SIM circuit design Keep the placement of U SIM card connector as close to the module as possible Keep the trace length a...

Page 51: ...s one USB 3 0 interface and one USB 2 0 interface which support SuperSpeed 5 Gbps on USB 3 0 and High Speed 480 Mbps on USB 2 0 modes The USB 3 0 interface is used for data communication with AP by default The USB 2 0 interface supports AT command communication data transmission software debugging firmware upgrade and voice over USB Table 12 Pin Description of USB Interface Pin Name Pin No I O Des...

Page 52: ... also these resistors should be placed close to each other The capacitors C1 and C2 should be placed near the module The capacitors C3 and C4 should be placed near the AP The extra stubs of trace must be as short as possible The following principles of USB interface should be complied with so as to meet USB 2 0 and USB 3 0 specifications It is important to route the USB 2 0 and 3 0 signal traces a...

Page 53: ...er therefore they cannot be used simultaneously 2 means under development 3 11 UART Interfaces The module provides three UART interfaces UART1 BT UART and debug UART UART1 and BT UART support RTS and CTS hardware flow control and are used for data transmission with peripherals UART1 and BT UART support 4800 9600 19200 38400 57600 115200 230400 460800 and 921600 bps baud rates and the default is 11...

Page 54: ...V UART interface A level translator TXS0104E Q1 provided by Texas Instruments visit http www ti com for more information is recommended The following figure shows a reference design VCCA VCCB OE A1 A2 A3 A4 NC GND B1 B2 B3 B4 NC VDD_1V8 CTS RTS RXD TXD 0 1 μF 0 1 μF CTS_MCU RTS_MCU RXD_MCU TXD_MCU VDD_MCU Translator Figure 22 Reference Circuit with Translator Chip Another example with transistor t...

Page 55: ...s 2 For the purpose of reducing power consumption it is recommended to switch off the power supply for VDD_1V8 in sleep mode 3 Please note that the module CTS is connected to the host CTS and the module RTS is connected to the host RTS 3 12 I2S and I2C Interfaces The module provides I2S and I2C interfaces for audio function design Table 17 Pin Definition of I2S Interface Pin Name Pin No I O Descri...

Page 56: ...with an external codec IC CDC_RST I2S_MCLK I2S_CLK I2S_WS I2S_DIN I2S_DOUT I2C1_SCL I2C1_SDA Module BIAS INP INN LOUTP LOUTN Codec RESET MCLK BCLK WCLK DOUT DIN SCL SDA 1 8V 2 2K 2 2K Figure 24 Reference Circuit of I2S and I2C Application with Audio Codec The module works as a master device pertaining to I2C interface 3 13 SDIO Interface The module provides an SDIO interface It is recommended to u...

Page 57: ...SDC1_DATA_1 50 IO SDIO data bit 1 SDC1_DATA_2 51 IO SDIO data bit 2 SDC1_DATA_3 52 IO SDIO data bit 3 SDC1_CMD 48 IO SDIO command SDC1_DATA_4 53 IO SDIO data bit 4 1 8 V power domain For eMMC configuration by default Can be configured to GPIO SDC1_DATA_5 55 IO SDIO data bit 5 SDC1_DATA_6 56 IO SDIO data bit 6 SDC1_DATA_7 58 IO SDIO data bit 7 SDC1_CLK 47 DO SDIO clock 1 8 V power domain for eMMC E...

Page 58: ...alue is 10 100 kΩ In order to improve signal quality it is recommended to add 0 Ω resistors R1 R9 and R11 in series between the module and eMMC Resistor R10 should be 30 35 Ω The bypass capacitors C1 C11 are reserved and not mounted by default All resistors and bypass capacitors should be placed close to the module It is important to route the SDIO signal traces with total grounding The impedance ...

Page 59: ...elated parameters of SPI timing are shown in the table below SPI_CS SPI_CLK SPI_MOSI SPI_MISO MSB 1 2 3 T t mov 4 t mis t mih t ch t cl Figure 26 SPI Timing Table 21 Parameters of SPI Interface Timing Pin Name Pin No I O Description Comment SPI1_CLK 216 DO SPI1 clock 1 8 V power domain Can be configured to GPIO If unused keep them open SPI1_CS 213 DO SPI1 chip select SPI1_MISO 219 DI SPI1 master i...

Page 60: ...VLAN tagging Can be used to connect to external Ethernet PHY like 88EA1512 or an external switch Table 22 Pin Definition of RGMII Interface t cl SPI clock low level time 9 0 ns t mov SPI master data output valid time 5 0 5 0 ns t mis SPI master data input setup time 5 0 ns t mih SPI master data input hold time 1 0 ns Pin Name Pin No I O Description Comment RGMII_MD_IO 10 IO RGMII MDIO management d...

Page 61: ..._TX_0 20 DO RGMII transmit data bit 0 RGMII_CTL_TX 21 DO RGMII transmit control RGMII_TX_1 22 DO RGMII transmit data bit 1 RGMII_TX_2 23 DO RGMII transmit data bit 2 RGMII_CK_TX 24 DO RGMII transmit clock RGMII_TX_3 25 DO RGMII transmit data bit 3 RGMII_PWR_EN 27 DO Enable external LDO to supply power to RGMII_PWR_IN 1 8 V power domain RGMII_PWR_IN 28 PI Power input for internal RGMII circuit 1 8 ...

Page 62: ...lication please follow the criteria below in the Ethernet PHY circuit design The I O voltage of RGMII matches with that of PHY The voltage of RGMII_INT and RGMII_RST matches with the I O voltage of PHY The typical power consumption of RGMII_PER_IN is 300 mA 1 8 V Keep RGMII data and control signals away from RF and VBAT traces Assure impedance of RGMII signals trace is 50 Ω 20 The length differenc...

Page 63: ...k Require differential impedance of 95 Ω PCIE_REFCLK_M 38 AO PCIe reference clock PCIE_TX_M 44 AO PCIe transmit PCIE_TX_P 46 AO PCIe transmit PCIE_RX_M 32 AI PCIe receive PCIE_RX_P 34 AI PCIe receive PCIE_CLKREQ 36 DI O PCIe clock request 1 8 V power domain PCIE_RST 39 DO PCIe reset PCIE_WAKE 30 DI PCIe wakeup Coexistence Interface COEX_UART_ RXD 67 DI LTE WLAN BT coexistence receive 1 8 V power d...

Page 64: ... The following figure shows a reference design for WLAN and BT interfaces application BT_UART_CTS 62 DO BT UART clear to send GPIOs PCM_SYNC 73 IO PCM data frame sync PCM_CLK 75 IO PCM data bit clock PCM_IN 76 DI PCM data input PCM_OUT 78 DO PCM data output Others interfaces WLAN_PWR_EN2 225 DO WLAN power supply enable control 2 1 8 V power domain WLAN_PWR_EN1 222 DO WLAN power supply enable contr...

Page 65: ..._WAKE PCIE_RST PCIE_REFCLKP PCIE_REFCLKM PCIE_RXM PCIE_RXP PCIE_TXP PCIE_TXM COEX_UART_ RXD COEX_UART_ TXD BT_UART_TXD BT_UART_RXD BT_UART_CTS BT_UART_RTS PCM_CLK PCM_SYNC PCM_IN PCM_OUT WLAN_EN BT_EN SLEEP_CLK R1 100K R2 100K VDD_EXT WLAN_PWR_EN1 WLAN_PWR_EN2 VDD_WIFI_VM VDD_WIFI_VH VDD_WIFI_VM VDD_WIFI_VH C1 100 nF C2 100 nF C3 100 nF C4 100 nF Figure 29 Reference Circuit for Connection with WLA...

Page 66: ...ls oscillators magnetic devices or RF signal traces It is important to route the PCIe differential traces in inner layer with ground shielding on not only upper and lower layers but also right and left sides 3 17 ADC Interfaces The module provides three analog to digital converter ADC interfaces The voltage value on ADC pins can be read via AT QADC port command through specifying port as 0 1 or 2 ...

Page 67: ...re powering on the module will force the module into emergency download mode when powered on In emergency download mode the module supports firmware upgrade over USB 2 0 interface Table 26 Pin Definition of USB_BOOT Interface Pin Name Pin No I O Description Comment USB_BOOT 83 DI Force the module into emergency download mode 1 8 V power domain Active high If unused keep it open The following figur...

Page 68: ...Open_Hardware_Design 67 92 Table 27 Pin Definition of GPIOs Pin Name Pin No I O Description Comment GPIO1 100 IO General purpose input output 1 8 V power domain If unused keep them open GPIO2 101 IO GPIO3 102 IO GPIO4 104 IO GPIO5 116 IO GPIO6 243 IO GPIO7 246 IO GPIO8 249 DO ...

Page 69: ... Definition The pin definition of Main Rx diversity antenna interfaces are shown below Table 28 Pin Definition of Main Rx diversity Antenna Interfaces Pin Name Pin No I O Description Comment ANT_MAIN 143 AI AO Main antenna interface 50 Ω impedance ANT_DIV 170 AI Receive diversity antenna interface 50 Ω impedance 4 1 2 Operating Frequency Table 29 Module Operating Frequencies 3GPP Band Transmit Rec...

Page 70: ...E FDD B29 B30 and B32 support Rx only 4 1 3 Reference Design of RF Antenna Interfaces A reference design of main and Rx diversity antenna interfaces is shown as below It is recommended to reserve a π type matching circuit for better RF performance and the π type matching components R1 C1 C2 and R2 C3 C4 should be placed as close to the antennas as possible The capacitors are not mounted by default...

Page 71: ...es should be controlled to 50 Ω The impedance of the RF traces is usually determined by the trace width W the materials dielectric constant the height from the reference ground to the signal layer H and the spacing between RF traces and grounds S Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance The following are reference designs of microstrip or ...

Page 72: ...d should be fully connected to ground The distance between the RF pins and the RF connector should be as short as possible and all the right angle traces should be changed to curved ones The recommended trace angle is 135 There should be clearance under the signal pin of the antenna connector or solder joint The reference ground of RF traces should be complete Meanwhile adding some ground vias aro...

Page 73: ...na Table 30 Antenna Requirements Type Requirements UMTS LTE VSWR 2 Efficiency 30 Max input power 50 W Input impedance 50 Ω Cable insertion loss 1 dB LTE FDD B5 B12 B13 B14 B26 B29 B71 Cable insertion loss 1 5 dB LTE FDD B2 B4 B25 B66 Cable insertion loss 2 dB LTE FDD B7 B30 4 2 2 Recommended RF Connector for Antenna Installation If RF connector is used for antenna connection it is recommended to u...

Page 74: ...Automotive Module Series AG521R NA QuecOpen Hardware Design AG521R NA_QuecOpen_Hardware_Design 73 92 Figure 36 Description of the HFM Connector For more details visit https www rosenbergerap com ...

Page 75: ...dule are listed in the following table Table 31 Absolute Maximum Ratings Parameter Min Max Unit VBAT_RF VBAT_BB 0 3 6 0 V USB_VBUS 0 3 5 5 V Peak Current of VBAT_BB 0 0 8 A Peak Current of VBAT_RF 0 2 0 A Voltage at Digital Pins 0 3 2 04 V Voltage at ADC0 0 1 91 V Voltage at ADC1 0 1 91 V 5 2 Power Supply Ratings Table 32 Power Supply Ratings Parameter Description Conditions Min Typ Max Unit VBAT ...

Page 76: ...odule remains fully functional and retains the ability to establish and maintain functions such as voice SMS data transmission and emergency call without any unrecoverable malfunction Radio spectrum and radio network will not be influenced while one or more specifications such as Pout may undergo a reduction in value exceeding the specified tolerances of 3GPP When the temperature returns to the no...

Page 77: ...ected 2 72 mA LTE FDD PF 64 USB suspend TBD mA LTE FDD PF 128 USB disconnected 3 57 mA LTE FDD PF 256 USB disconnected 2 41 mA LTE data transfer GNSS OFF LTE FDD B2 23 0 dBm 650 mA LTE FDD B4 23 0 dBm 620 mA LTE FDD B5 23 0 dBm 594 mA LTE FDD B7 23 0 dBm 730 mA LTE FDD B12 23 0 dBm 573 mA LTE FDD B13 23 0 dBm 543 mA LTE FDD B14 23 0 dBm 618 mA LTE FDD B25 23 0 dBm 650 mA LTE FDD B26 23 0 dBm 620 m...

Page 78: ...4 23 dBm 2 dB 39 dBm LTE TDD B25 23 dBm 2 dB 39 dBm LTE TDD B26 23 dBm 2 dB 39 dBm LTE TDD B66 23 dBm 2 dB 39 dBm LTE TDD B71 23 dBm 2 dB 39 dBm 5 6 RF Receiving Sensitivity Table 36 RF Receiving Sensitivity Unit dBm Frequency Receive Sensitivity Typ Primary Diversity SIMO 3GPP SIMO LTE FDD B2 10 MHz 98 7 99 1 101 5 94 3 dBm LTE FDD B4 10 MHz 98 2 99 5 101 7 96 3 dBm LTE FDD B5 10 MHz 99 8 100 3 1...

Page 79: ...y to ESD sensitive components Proper ESD handling and packaging procedures must be applied throughout the processing handling and operation of any application that incorporates the module The following table shows the module electrostatic discharge characteristics Table 37 Electrostatic Discharge Characteristics Tested Points Contact Discharge Air Discharge Unit VBAT GND 8 10 kV Antenna Interfaces...

Page 80: ...ers application demands the heatsink can be mounted on the top of the module or the opposite side of the PCB area where the module is mounted or both of them The heatsink should be designed with as many fins as possible to increase heat dissipation area Meanwhile a thermal pad with high thermal conductivity should be used between the heatsink and module PCB The following shows two kinds of heatsin...

Page 81: ...utput power and data rate When the maximum BB chip temperature reaches or exceeds 118 C the module will disconnect from the network and it will recover to network connected state after the maximum temperature falls below 118 C Therefore the thermal design should be maximally optimized to make sure the maximum BB chip temperature always maintains below 105 C Customers can execute AT QTEMP command a...

Page 82: ...are_Design 81 92 6 Mechanical Dimensions This chapter describes the mechanical dimensions of the module All dimensions are measured in millimeter mm and the dimensional tolerances are 0 05 mm unless otherwise specified 6 1 Mechanical Dimensions Figure 39 Module Top and Side Dimensions ...

Page 83: ...Module Series AG521R NA QuecOpen Hardware Design AG521R NA_QuecOpen_Hardware_Design 82 92 Figure 40 Module Bottom Dimensions Top View The package warpage level of the module conforms to JEITA ED 7306 standard NOTE ...

Page 84: ...dware Design AG521R NA_QuecOpen_Hardware_Design 83 92 6 2 Recommended Footprint Figure 41 Recommended Footprint Top View For convenient maintenance of the module please keep about 3 mm between the module and other components on the motherboard NOTE ...

Page 85: ...dware Design AG521R NA_QuecOpen_Hardware_Design 84 92 6 3 Top and Bottom Views Figure 42 Top View of the Module Figure 43 Bottom View of the Module These are renderings of the module For authentic appearance see the module received from Quectel NOTE ...

Page 86: ...removed the module must be processed in reflow soldering or other high temperature operations within 24 hours Otherwise the module should be stored in an environment where the relative humidity is less than 10 e g a drying cabinet 4 The module should be pre baked to avoid blistering cracks and inner layer separation in PCB under the following circumstances The module is not stored in Recommended S...

Page 87: ...e solder paste on the surface of stencil thus making the paste fill the stencil openings and then penetrate to the PCB The force on the squeegee should be adjusted properly so as to produce a clean stencil surface on a single pass To ensure the module soldering quality the thickness of stencil for the module is recommended to be 0 15 0 18 mm For more details see document 6 It is suggested that the...

Page 88: ...ne reel is 10 56 meters long and contains 220 modules The figures below show the packaging details measured in mm Factor Recommendation Soak Zone Max slope 1 3 C s Soak time between A and B 150 C and 200 C 70 120 s Reflow Zone Max slope 2 3 C s Reflow time D over 220 C 45 70 s Max temperature 238 246 C Cooling down slope 1 5 to 3 C s Reflow Cycle Max reflow cycle 1 ...

Page 89: ...Automotive Module Series AG521R NA QuecOpen Hardware Design AG521R NA_QuecOpen_Hardware_Design 88 92 Figure 45 Tape Specifications Figure 46 Reel Specifications ...

Page 90: ...ctel_RF_Layout_Application_Note RF Layout Application Note 5 Quectel_LTE_Module_Thermal_Design_Guide Thermal Design Guide for Quectel LTE LTE Standard LTE A Automotive modules 6 Quectel_Module_Secondary_SMT_Application_Note Quectel Module Secondary SMT Application Note 7 Quectel_AG52xR_Series_QuecOpen_Reference_Design AG52xR Series QuecOpen Reference Design Table 40 Terms and Abbreviations Abbrevi...

Page 91: ...D Frequency Division Duplex FR Full Rate GLONASS GLObalnaya NAvigatsionnaya Sputnikovaya Sistema the Russian Global Navigation Satellite System GMSK Gaussian Minimum Shift Keying GPS Global Positioning System GSM Global System for Mobile Communications HR Half Rate HSPA High Speed Packet Access HSDPA High Speed Downlink Packet Access HSUPA High Speed Uplink Packet Access I O Input Output Inorm Nor...

Page 92: ...PSK Quadrature Phase Shift Keying RF Radio Frequency RHCP Right Hand Circularly Polarized Rx Receive SIMO Single Input Multiple Output SMS Short Message Service TDD Time Division Duplexing TDMA Time Division Multiple Access TD SCDMA Time Division Synchronous Code Division Multiple Access TX Transmitting Direction UL Uplink UMTS Universal Mobile Telecommunications System URC Unsolicited Result Code...

Page 93: ...nimum Input Low Level Voltage Value VImax Absolute Maximum Input Voltage Value VImin Absolute Minimum Input Voltage Value VOHmax Maximum Output High Level Voltage Value VOHmin Minimum Output High Level Voltage Value VOLmax Maximum Output Low Level Voltage Value VOLmin Minimum Output Low Level Voltage Value VRWM Reserve Stand Off Voltage VSWR Voltage Standing Wave Ratio WCDMA Wideband Code Division...

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