Automotive Module Series
AG521R-NA QuecOpen
Hardware Design
AG521R-NA_QuecOpen_Hardware_Design 53 / 92
Table 15: Pin Definition of Debug UART Interface
Pin Name
Pin No.
I/O
Description
Comment
DBG_TXD
107
DO
Debug UART transmit
1.8 V power domain.
DBG_RXD
110
DI
Debug UART receive
1.8 V power domain.
Table 16: Logic Levels of Digital I/O
Parameter
Min.
Max.
Unit
V
IL
-0.3
0.63
V
V
IH
1.17
2.1
V
V
OL
0
0.45
V
V
OH
1.35
1.8
V
The module provides 1.8 V UART interfaces. A level translator should be used if customers’ application is
equipped with a 3.3 V UART interface. A level translator TXS0104E-Q1 provided by
Texas Instruments
(visit
http://www.ti.com for more information) is recommended. The following figure shows a reference design.
VCCA
VCCB
OE
A1
A2
A3
A4
NC
GND
B1
B2
B3
B4
NC
VDD_1V8
CTS
RTS
RXD
TXD
0.1
μ
F
0.1
μ
F
CTS_MCU
RTS_MCU
RXD_MCU
TXD_MCU
VDD_MCU
Translator
Figure 22: Reference Circuit with Translator Chip
Another example with transistor translation circuit is shown as below. The circuit design of dotted line section can
refer to the design of solid line section, in terms of both module input and output circuit designs, but please pay
BT_UART_RXD
63
DI
BT UART receive
Can be configured to GPIOs
BT_UART_RTS
61
DI
BT UART request to send
BT_UART_CTS
62
DO
BT UART clear to send
