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Quectel LTE-A Series, Hardware Design

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LTE-A  Module  Series 

                                                                                                  EG18  Hardware  Design

 

 

EG18_Hardware_Design                                                                                                                          74 / 104 

 
 

 

 

5.1.3.  Reference Design of RF Antenna Interfaces 

A  reference  design  of  ANT_MAIN,  ANT_DIV,  ANT_MIMO1  and  ANT_MIMO2  interfaces  is  shown  as 

below.  It  should  reser

ve  a  π-type  matching  circuit  for  better  RF  performance.  The  π-type  matching 

components (R1/C1/C2, R2/C3/C4, R3/C5/C6, R4/C7/C8) should be placed as close to the antennas as 

possible and are mounted according to the actual debugging. C1 to C8 are not mounted and 

a 0Ω resistor 

is mounted on R1 to R4 respectively by default. 

ANT_MAIN

R1    0R

C1

Module

Main
Antenna

NM

C2

NM

R3    0R

C5

MIMO 
Antenna

NM

C6

NM

ANT_DIV

R2    0R

C3

NM

C4

NM

ANT_MIMO1

C7

NM

C8

NM

ANT_MIMO2

MIMO 
Antenna

Diversity
Antenna

R4    0R

 

Figure 36: Reference Circuit of RF Antenna Interfaces 

 

Please keep a proper distance between the main antenna and the Rx-diversity antenna to improve the 

receiving sensitivity. 

LTE B30 

2305~2315 

2350~2360 

MHz 

LTE B41 

2496~2689.9 

2496~2689.9 

MHz 

LTE B66 

1710~1780 

2110~2200 

MHz 

LTE B71 

617~652 

663~698 

MHz 

NOTE 

Summary of Contents for LTE-A Series

Page 1: ...EG18 Hardware Design LTE A Module Series Rev EG18_Hardware_Design_V1 1 Date 2019 12 21 Status Released www quectel com ...

Page 2: ...HE INFORMATION PROVIDED IS BASED UPON CUSTOMERS REQUIREMENTS QUECTEL MAKES EVERY EFFORT TO ENSURE THE QUALITY OF THE INFORMATION IT MAKES AVAILABLE QUECTEL DOES NOT MAKE ANY WARRANTY AS TO THE INFORMATION CONTAINED HEREIN AND DOES NOT ACCEPT ANY LIABILITY FOR ANY INJURY LOSS OR DAMAGE OF ANY KIND INCURRED BY USE OF OR RELIANCE UPON THE INFORMATION ALL INFORMATION SUPPLIED HEREIN IS SUBJECT TO CHAN...

Page 3: ...IA Initial 1 1 2019 12 21 Archibald JIANG Xavier XIA 1 Updated the current consumption and sensitivity data of EG18 NA 2 Updated the timing information of powering on powering off resetting U SIM and USB in Chapter 3 3 Added description about the position of the temperature sensors corresponding to the temperatures obtained with AT QTEMP command in Chapter 6 8 ...

Page 4: ...ion 33 3 4 1 3 USB Application with USB Suspend Resume and RI Function 34 3 4 1 4 USB Application without USB Suspend Function 34 3 4 2 Airplane Mode 35 3 5 Power Supply 36 3 5 1 Power Supply Pins 36 3 5 2 Decrease Voltage Drop 37 3 5 3 Reference Design for Power Supply 38 3 5 4 Monitor the Power Supply 38 3 6 Turn on and off Scenarios 39 3 6 1 Turn on the Module Through PWRKEY 39 3 6 2 Turn off t...

Page 5: ...2 Operating Frequencies 72 5 1 3 Reference Design of RF Antenna Interfaces 74 5 2 GNSS Antenna Interface 75 5 2 1 Pin Definition 75 5 2 2 GNSS Frequency 75 5 2 3 Reference Design of GNSS Antenna Interface 76 5 3 Reference Design of RF Layout 77 5 4 Antenna Installation 78 5 4 1 Antenna Requirements 78 5 4 2 Recommended RF Connector for Antenna Installation 79 6 Electrical Reliability and Radio Cha...

Page 6: ...chanical Dimensions 93 7 1 Mechanical Dimensions of the Module 93 7 2 Recommended Footprint 95 7 3 Design Effect Drawings of the Module 96 8 Storage Manufacturing and Packaging 97 8 1 Storage 97 8 2 Manufacturing and Soldering 98 8 3 Packaging 99 9 Appendix A References 101 ...

Page 7: ...BLE 19 PIN DEFINITION OF THE ADC INTERFACES 58 TABLE 20 CHARACTERISTICS OF ADC INTERFACES 58 TABLE 21 PIN DEFINITION OF NETWORK STATUS ACTIVITY INDICATOR 58 TABLE 22 WORKING STATE OF THE NETWORK STATUS ACTIVITY INDICATOR 59 TABLE 23 PIN DEFINITION OF STATUS 60 TABLE 24 RI BEHAVIORS 61 TABLE 25 PIN DEFINITION OF THE PCIE INTERFACE 61 TABLE 26 PIN DEFINITION OF SDIO INTERFACE 65 TABLE 27 PIN DEFINIT...

Page 8: ... TABLE 43 RF OUTPUT POWER 87 TABLE 44 EG18 EA CONDUCTED RF RECEIVING SENSITIVITY 87 TABLE 45 EG18 NA CONDUCTED RF RECEIVING SENSITIVITY 88 TABLE 46 ELECTROSTATIC DISCHARGE CHARACTERISTICS 89 TABLE 47 RECOMMENDED THERMAL PROFILE PARAMETERS 98 TABLE 48 RELATED DOCUMENTS 101 TABLE 49 TERMS AND ABBREVIATIONS 101 ...

Page 9: ... REFERENCE CIRCUIT OF A U SIM INTERFACE WITH AN 8 PIN U SIM CARD CONNECTOR 45 FIGURE 19 REFERENCE CIRCUIT OF A U SIM INTERFACE WITH A 6 PIN U SIM CARD CONNECTOR 45 FIGURE 20 TIMING OF U SIM 46 FIGURE 21 TIMING OF HOT PLUG 46 FIGURE 22 REFERENCE CIRCUIT OF USB APPLICATION 48 FIGURE 23 TIMING OF USB ENUMERATION 49 FIGURE 24 LEVEL TRANSLATION REFERENCE CIRCUIT WITH AN IC 52 FIGURE 25 LEVEL TRANSLATIO...

Page 10: ...0 FIGURE 45 REFERENCE DESIGN OF HEATSINK HEATSINK AT THE TOP OF THE MODULE 90 FIGURE 46 REFERENCE DESIGN OF HEATSINK HEATSINK AT THE BACKSIDE OF PCB 90 FIGURE 47 RESPONSE OF AT QTEMP 91 FIGURE 48 TEMPERATURE SENSOR DISTRIBUTION 92 FIGURE 49 MODULE TOP AND SIDE DIMENSIONS UNIT MM 93 FIGURE 50 MODULE BOTTOM DIMENSIONS TOP VIEW UNIT MM 94 FIGURE 51 RECOMMENDED FOOTPRINT TOP VIEW UNIT MM 95 FIGURE 52 ...

Page 11: ...are interfaces which are connected to customers applications This document helps customers quickly understand interface specifications electrical and mechanical details as well as other related technical information of EG18 module Associated with relevant application notes and user guides the module will be used to design and set up mobile applications easily ...

Page 12: ...lt the airline staff for more restrictions on the use of wireless devices on aircraft Wireless devices may cause interference with sensitive medical equipment so please be aware of the restrictions on the use of wireless devices when in hospitals clinics or other healthcare facilities Cellular terminals or mobiles operating over radio signals and cellular network cannot be guaranteed to connect in...

Page 13: ...icated variant based on the region or operator The following table shows the frequency bands CA combinations 3 and GNSS types of EG18 module Table 1 Frequency Bands CA Combinations and GNSS Types of EG18 Module Mode EG18 EA EG18 NA LTE FDD with Rx diversity B1 B3 B5 B7 B8 B20 B28 B2 B4 B5 B7 B12 B13 B14 B25 B26 B29 4 B30 B66 B71 LTE TDD with Rx diversity B38 B40 B41 B41 2 CA DL B1 B1 B3 B5 B7 B8 B...

Page 14: ... phone and tablet PC EG18 is an SMD type module and can be embedded in applications through its 299 LGA pins 3 CA DL B1 B3 B3 B5 B7 B8 B20 B28 B38 B41 B1 B40 B40 B1 B41 B41 B1 B7 B20 B3 B3 B7 B20 B28 B3 B7 B7 B8 B20 B28 B3 B40 B40 B3 B41 B41 B7 B7 B20 B28 B40 B40 B40 B41 B41 B41 B2 B4 B5 B13 B71 B2 B5 B66 B2 B12 B30 B2 B13 B66 B2 B7 B12 B66 B4 B30 B5 B12 B29 B4 B7 B12 B30 B66 B5 B12 B29 B2 B2 B5 B...

Page 15: ...90 6Mbps UL UMTS Features Support 3GPP R9 DC HSDPA DC HSUPA HSPA HSDPA HSUPA and WCDMA Support QPSK 16 QAM and 64 QAM modulation DC HSDPA Max 42Mbps DC HSUPA Max 11 5Mbps WCDMA Max 384Kbps DL 384Kbps UL Internet Protocol Features Support PPP QMI TCP UDP FTP HTTP NTP PING HTTPS SMTP MMS FTPS SMTPS SSL protocols Support PAP Password Authentication Protocol and CHAP Challenge Handshake Authentication...

Page 16: ...d for Bluetooth communication and can be multiplexed into SPI interface 115200bps baud rate PCIe 1 Interface Comply with PCI Express Specification Revision 2 1 and support 5Gbps per lane Used for data transmission Rx diversity Support LTE WCDMA Rx diversity and LTE HO diversity GNSS Features Gen9HT Lite of Qualcomm Protocol NMEA 0183 AT Commands Comply with 3GPP TS 27 007 and 27 005 and Quectel en...

Page 17: ... tolerances When the temperature returns to normal operating temperature levels the module will meet 3GPP specifications again 2 3 Functional Diagram The following figure shows a block diagram of EG18 and illustrates the major functional parts Power management Baseband LPDDR2 SDRAM NAND Flash Radio frequency Peripheral interfaces PMIC Transceiver NAND Flash LPDDR2 SDRAM Tx Rx Blocks ANT_DIV ANT_MA...

Page 18: ... 104 2 4 Evaluation Board To help with the development of applications with EG18 Quectel supplies the evaluation board EVB USB to RS 232 converter cable earphone antenna and other peripherals to control or test the module For more details please refer to document 2 ...

Page 19: ...following application interfaces and indication signals of EG18 Power supply U SIM interfaces USB interface UART interfaces SPI interface 1 PCM and I2C interfaces ADC interfaces Network status indication Operation status indication RI Behaviors PCIe interface SDIO interface Antenna tuner control interfaces USB_BOOT interface GPIOs 1 means under development 2 1 SPI interface is multiplexed from BT ...

Page 20: ...Pins U SIM Pins USB Pins I2C Pins SDIO Pins ADC Pins UART Pins SPI Pins ANT Pins CLK Pins RESET_N PWRKEY BT_EN WLAN_PWR_EN USIM1_DET USIM1_CLK USIM1_DATA USIM1_VDD USIM1_RST USB_VBUS USB_DM USB_DP USB_ID USB_SS_TX_M USB_SS_TX_P USB_SS_RX_P USB_SS_RX_M I2C_SDA I2C_SCL SD_VDD SD_DATA2 SD_DATA3 SD_DATA0 SD_DATA1 SD_CMD SD_DET SD_CLK CTS RTS RXD DCD TXD RI DTR PCM_SYNC PCM_CLK PCM_IN PCM_OUT USIM2_DAT...

Page 21: ...escription AI Analog Input AO Analog Output DI Digital Input DO Digital Output IO Bidirectional OD Open Drain PI Power Input PO Power Output Power Supply Pin Name Pin No I O Description DC Characteristics Comment VBAT_BB 155 156 PI Power supply for the module s baseband part Vmax 4 3V Vmin 3 3V Vnorm 3 8V It must be able to provide sufficient current up to 1 2A VBAT_RF 85 86 87 88 PI Power supply ...

Page 22: ...t Vnorm 2 85V IOmax 120mA GND 10 13 16 17 24 30 31 35 39 44 45 54 55 63 64 69 70 75 76 81 84 89 90 92 94 96 100 102 106 108 112 114 118 120 126 128 133 141 142 148 153 154 157 158 167 174 177 178 181 184 187 191 196 202 208 214 299 Ground Turn on off Pin Name Pin No I O Description DC Characteristics Comment RESET_N 1 DI Reset the module VIHmax 2 1V VIHmin 1 3V VILmax 0 5V 1 8V power domain Pulled...

Page 23: ...used keep it open U SIM Interfaces Pin Name Pin No I O Description DC Characteristics Comment USIM1_DET 25 DI U SIM1 card insertion detection VILmin 0 3V VILmax 0 6V VIHmin 1 2V VIHmax 2 0V 1 8V power domain If unused keep it open USIM1_VDD 26 PO Power supply for U SIM1 card For 1 8V U SIM Vmax 1 9V Vmin 1 7V For 3 0V U SIM Vmax 3 05V Vmin 2 75V IOmax 50mA Either 1 8V or 3 0V is supported by the m...

Page 24: ...Data signal of U SIM2 card For 1 8V U SIM VILmax 0 36V VIHmin 1 26V VOLmax 0 4V VOHmin 1 45V For 3 0V U SIM VILmax 0 57V VIHmin 2V VOLmax 0 4V VOHmin 2 3V If U SIM2 interface is unused keep it open USIM2_DET 78 DI U SIM2 card insertion detection VILmin 0 3V VILmax 0 6V VIHmin 1 2V VIHmax 2 0V 1 8V power domain If U SIM2 interface is unused keep it open USIM2_RST 79 DO Reset signal of U SIM2 card F...

Page 25: ...P 40 AI USB 3 0 super speed receiving USB_SS_ RX_M 41 AI USB 3 0 super speed receiving USB_ID 36 DI OTG identification VILmin 0 3V VILmax 0 6V VIHmin 1 2V VIHmax 2 0V 1 8V power domain If unused keep it open OTG_PWR_EN 143 DO OTG power control VOLmax 0 45V VOHmin 1 35V SDIO Interface Pin Name Pin No I O Description DC Characteristics Comment SD_VDD 46 PO SD card application SDIO pull up power sour...

Page 26: ...in No I O Description DC Characteristics Comment CTS 56 DO Clear to send VOLmax 0 45V VOHmin 1 35V 1 8V power domain If unused keep it open RTS 57 DI Request to send VILmin 0 3V VILmax 0 6V VIHmin 1 2V VIHmax 2 0V 1 8V power domain If unused keep it open RXD 58 DI Receive data VILmin 0 3V VILmax 0 6V VIHmin 1 2V VIHmax 2 0V 1 8V power domain If unused keep it open DCD 59 DO Data carrier detection ...

Page 27: ...stics Comment BT_EN 3 DO BT function enable control VOLmax 0 45V VOHmin 1 35V 1 8V power domain If unused keep it open BT_TXD 163 DO Transmit data VOLmax 0 45V VOHmin 1 35V 1 8V power domain If unused keep it open BT UART interface pin by default Can be multiplexed into SPI_MOSI BT_CTS 164 DO Clear to send VOLmax 0 45V VOHmin 1 35V 1 8V power domain If unused keep it open BT UART interface pin by ...

Page 28: ...nput signal If unused keep it open PCM_IN 66 DI PCM data input VILmin 0 3V VILmax 0 6V VIHmin 1 2V VIHmax 2 0V 1 8V power domain If unused keep it open PCM_CLK 67 IO PCM clock VOLmax 0 45V VOHmin 1 35V VILmin 0 3V VILmax 0 6V VIHmin 1 2V VIHmax 2 0V 1 8V power domain In master mode it is an output signal In slave mode it is an input signal If unused keep it open PCM_OUT 68 DO PCM data output VOLma...

Page 29: ...tence signal VILmin 0 3V VILmax 0 6V VIHmin 1 2V VIHmax 2 0V 1 8V power domain If unused keep it open WLAN_EN 149 DO WLAN function enable control VOLmax 0 45V VOHmin 1 35V 1 8V power domain Active high If unused keep it open WAKE_ON_ WIRELESS 160 DI Wake up the host EG18 by an external Wi Fi module VILmin 0 3V VILmax 0 6V VIHmin 1 2V VIHmax 2 0V 1 8V power domain Active low If unused keep it open ...

Page 30: ...6V VIHmin 1 2V VIHmax 2 0V In master mode it is an input signal In slave mode it is an output signal If unused keep it open PCIE_RST_N 189 IO PCIe reset VOLmax 0 45V VOHmin 1 35V VILmin 0 3V VILmax 0 6V VIHmin 1 2V VIHmax 2 0V In master mode it is an output signal In slave mode it is an input signal If unused keep it open PCIE_WAKE_N 190 IO PCIe wake up VOLmax 0 45V VOHmin 1 35V VILmin 0 3V VILmax...

Page 31: ... them open GPIO_4 161 IO GPIO_5 172 IO Other Pins Pin Name Pin No I O Description DC Characteristics Comment USB_BOOT 140 DI Force the module to enter emergency download mode VILmin 0 3V VILmax 0 6V VIHmin 1 2V VIHmax 2 0V 1 8V power domain Active high If unused keep it open SLEEP_IND 144 DO Sleep indication VOLmax 0 45V VOHmin 1 35V 1 8V power domain If unused keep it open WAKEUP_IN 150 DI Sleep ...

Page 32: ... consumption is decided by network setting and data transfer rate Minimum Functionality Mode AT CFUN 0 command can set the module to a minimum functionality mode without removing the power supply In this case both RF function and U SIM card will be invalid Airplane Mode AT CFUN 4 command or driving W_DISABLE pin to low level can set the module to airplane mode In this case RF function will be inva...

Page 33: ...sumption in sleep mode The longer the DRX cycle is the lower the current consumption will be Current Consumption Run Time DRX OFF ON OFF ON OFF ON OFF ON OFF Figure 3 DRX Run Time and Current Consumption in Sleep Mode The following sections describes power saving procedure of EG18 3 4 1 1 UART Application If the host communicates with the module via UART interfaces both of the following preconditi...

Page 34: ... about RI behaviors 3 4 1 2 USB Application with USB Remote Wakeup Function If the host supports USB suspend resume and remote wakeup function the following three preconditions must be met to let the module enter sleep mode Keep DTR at high level pulled up by default Execute AT QSCLK 1 command to enable the sleep mode The host s USB bus which is connected with the module s USB interface has entere...

Page 35: ...mmand to enable the sleep mode The host s USB bus which is connected with the module s USB interface has entered into suspend state The following figure shows the connection between the module and the host USB_VBUS USB Interface VDD USB Interface Module Host GND GND RI EINT Figure 6 Sleep Mode Application with RI Sending data to EG18 through USB will wake up the module When EG18 has a URC to repor...

Page 36: ... 4 2 Airplane Mode EG18 provides a W_DISABLE signal to disable or enable airplane mode through hardware operation The W_DISABLE pin is pulled up by default Driving it to low level will make the module enter into airplane mode In airplane mode RF function will be disabled The RF function can also be enabled or disabled through AT commands The following table shows the RF function status of the modu...

Page 37: ... domains for VBAT Four VBAT_RF pins for RF part Two VBAT_BB pins for baseband part The following table shows details of VBAT pins and ground pins Table 7 VBAT and GND Pins Low Level AT CFUN 0 AT CFUN 1 AT CFUN 4 RF Disabled Airplane mode Pin Name Pin No Description Min Typ Max Unit VBAT_RF 85 86 87 88 Power supply for the module s RF part 3 3 3 8 4 3 V VBAT_BB 155 156 Power supply for the module s...

Page 38: ...mmended to use three ceramic capacitors 100nF 33pF 10pF for composing of the MLCC array and to place these capacitors close to VBAT pins The main power supply from an external application has to be a single voltage source and can be expanded to two sub paths with star structure The width of VBAT_BB trace should be no less than 1mm and the width of VBAT_RF trace should be no less than 2mm In princi...

Page 39: ...buck converter is preferred to be used as the power supply The following figure shows a reference design for 5V input power source In this design output of the power supply is about 3 8V and the maximum load current is 3A DC_IN MIC29302WU IN OUT EN GND ADJ 2 4 1 3 5 VBAT 100nF 470μF 100nF 100K 47K 470μF 470R 51K 1 1 4 7K 47K VBAT_EN Figure 10 Reference Circuit of Power Supply To avoid damages to t...

Page 40: ...g the PWRKEY pin to a low level voltage for at least 500ms It is recommended to use an open drain collector driver to control the PWRKEY After STATUS pin outputs a high level PWRKEY can be released A simple reference circuit is illustrated by the following figure Turn on pulse PWRKEY 4 7K 47K 500ms Figure 11 Turn on the Module with a Driving Circuit Pin Name Pin No Description DC Characteristics C...

Page 41: ...SD protection A reference circuit is shown by the following figure PWRKEY S1 Close to S1 TVS Figure 12 Turn on the Module Using a Button The timing of turn on scenario is illustrated by the following figure VIL 0 5V VIH 1 3V VBAT PWRKEY 500ms RESET_N STATUS Inactive Active UART NOTE 11 5s 13s VDD_EXT VDD_RF 17s 100ms USIM_VDD 16s 29ms Figure 13 Timing of Turning on the Module Please ensure that VB...

Page 42: ...0ms then the module will execute power down procedure after the PWRKEY is released The timing of turn off scenario is illustrated by the following figure VBAT PWRKEY 800ms RUNNING Power down procedure OFF Module Status STATUS 30s VDD_EXT VDD_RF 1 5s 10s USIM_VDD 1 6s Figure 14 Timing of Turning off the Module 3 6 2 2 Turn off the Module Through AT Command It is also a safe way to use AT QPOWD comm...

Page 43: ...f command Otherwise the module will be turned on again after a successful turning off 3 7 Reset the Module The module can be reset by driving RESET_N pin to a low level voltage for 250ms 600ms and then releasing it Table 9 RESET_N Pin Description An open drain collector driver or button can be used to control the RESET_N pin A reference circuit is shown as below Reset pulse RESET_N 4 7K 47K 250ms ...

Page 44: ... following figure VIL 0 5V VIH 1 3V VBAT 250ms Resetting Module Status Running RESET_N Restart 600ms 204ms VDD_RF 212 5ms VDD_EXT 205ms USIM_VDD 16s 2 5ms 17s Figure 17 Timing of Resetting the Module 1 RESET_N can only be used when the module failed to be turned off either by AT QPOWD command or PWRKEY 2 Please ensure that there is no capacitor with high capacitance on PWRKEY and RESET_N pins NOTE...

Page 45: ...AT QSIMDET command Pin Name Pin No I O Description Comment USIM1_DET 25 DI U SIM1 card insertion detection USIM1_VDD 26 PO Power supply for U SIM1 card Either 1 8V or 3 0V is supported by the module automatically USIM1_CLK 27 DO Clock signal of U SIM1 card USIM1_RST 28 DO Reset signal of U SIM1 card USIM1_DATA 29 IO Data signal of U SIM1 card USIM2_VDD 74 PO Power supply for U SIM2 card Either 1 8...

Page 46: ...5K NM NM NM CD1 CD2 Figure 18 Reference Circuit of a U SIM Interface with an 8 Pin U SIM Card Connector If U SIM card detection function is not needed please keep USIM_DET pins unconnected A reference circuit for a U SIM interface with a 6 pin U SIM card connector is illustrated by the following figure Module USIM_VDD USIM_RST USIM_CLK USIM_DATA 22R 22R 22R 100nF U SIM Card Connector GND VCC RST C...

Page 47: ...MDET 1 0 is set the scenario of hot plug is illustrated by the following figure USIM_VDD 20 8ms 1 1ms 1 7ms USIM_DATA USIM_CLK USIM_RST 5 8ms USIM_DET 103ms ATR Figure 21 Timing of Hot Plug In order to enhance the reliability and availability of the U SIM card in applications please follow the criteria below in the U SIM circuit design Keep the U SIM card connector as close as possible to the modu...

Page 48: ...ard connector 3 9 USB Interface EG18 provides one integrated Universal Serial Bus USB interface which complies with the USB 3 0 and USB 2 0 specifications It supports super speed 5Gbps on USB 3 0 and high speed 480Mbps and full speed 12Mbps modes on USB 2 0 The USB interface is used for AT command communication data transmission GNSS NMEA sentence output software debugging firmware upgrade and voi...

Page 49: ... R1 R2 Close to Module R3 R4 Test Points ESD Array NM_0R NM_0R 0R 0R Minimize these stubs Module Host USB_VBUS VDD USB_SS_TX_P USB_SS_TX_M USB_SS_RX_P USB_SS_RX_M C1 C3 C4 100nF 100nF 100nF 100nF USB_SS_RX_P USB_SS_RX_M USB_SS_TX_P USB_SS_TX_M USB_ID GPIO C2 Figure 22 Reference Circuit of USB Application In order to ensure the signal integrity of USB data lines C1 and C2 have been installed in the...

Page 50: ...maximum length of each differential data pair TX RX is recommended to be less than 100mm and each differential data pair matching should be less than 0 7mm 5ps Do not route signal traces under crystals oscillators magnetic devices PCIe and RF signal traces It is important to route the USB differential traces in inner layer of the PCB and surround the traces with ground on that layer and with groun...

Page 51: ...115200bps baud rate It is used for Linux console and log output BT UART interface supports 115200bps baud rate It is used for BT communication and can be multiplexed into SPI interface means under development 3 10 1 Main UART Interface The following table shows the main UART interface pin definition Table 12 Pin Definition of Main UART Interface Pin Name Pin No I O Description Comment CTS 56 DO Cl...

Page 52: ...ART interfaces A level translator should be used if the application is equipped with a 3 3V UART interface The logic levels are described in the following table Table 15 Logic Levels of Digital I O Pin Name Pin No I O Description Comment DBG_RXD 136 DI Receive data 1 8V power domain DBG_TXD 137 DO Transmit data 1 8V power domain Pin Name Pin No I O Description Comment BT_EN 3 DO BT function enable...

Page 53: ...reference design VCCA VCCB OE A1 A2 A3 A4 A5 A6 A7 A8 GND B1 B2 B3 B4 B5 B6 B7 B8 VDD_EXT RI DCD RTS RXD DTR CTS TXD 51K 51K 0 1μF 0 1μF RI_MCU DCD_MCU RTS_MCU TXD_MCU DTR_MCU CTS_MCU RXD_MCU VDD_MCU Translator VDD_EXT 10K 120K Figure 24 Level Translation Reference Circuit with an IC Please visit http www ti com for more information VIH 1 2 2 0 V VOL 0 0 45 V VOH 1 35 1 8 V ...

Page 54: ...EXT 4 7K GND 1nF 1nF Figure 25 Level Translation Reference Circuit with MOSFETs Transistor circuit solution is not suitable for applications with high baud rates exceeding 460kbps 3 11 SPI Interface EG18 provides one SPI interface multiplexed from BT UART interface The interface only supports master mode with a maximum clock frequency up to 50MHz The following table shows the pin definition of SPI...

Page 55: ...listed in the following table Table 17 Parameters of SPI Interface Timing means under development BT_RXD 165 DI Can be multiplexed into SPI_MISO BT_RTS 166 DI Can be multiplexed into SPI_CS Parameter Description Min Typ Max Unit T SPI clock period 20 0 ns t ch SPI clock high level time 9 0 ns t cl SPI clock low level time 9 0 ns t mov SPI master data output valid time 5 0 5 0 ns t mis SPI master d...

Page 56: ...n this mode PCM interface supports 256kHz 512kHz 1024kHz or 2048kHz PCM_CLK at 8kHz PCM_SYNC and also supports 4096kHz PCM_CLK at 16kHz PCM_SYNC In auxiliary mode the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising edge The PCM_SYNC rising edge represents the MSB In this mode PCM interface operates with a 256kHz PCM_CLK and an 8kHz 50 duty cycle PCM_SYNC only EG18 ...

Page 57: ...68 DO PCM data output 1 8V power domain If unused keep it open PCM_SYNC 65 IO PCM data frame synchronization signal 1 8V power domain In master mode it is an output signal In slave mode it is an input signal If unused keep it open PCM_CLK 67 IO PCM data clock 1 8V power domain In master mode it is an output signal In slave mode it is an input signal If unused keep it open I2C_SDA 42 OD I2C serial ...

Page 58: ...CL I2C_SDA Module VDD_EXT 4 7K 4 7K BCLK LRCK DAC ADC SCL SDA BIAS MICBIAS INP INN LOUTP LOUTN Codec Figure 29 Reference Circuit of PCM Application with Audio Codec 1 It is recommended to reserve an RC R 22Ω C 22pF circuit on the PCM lines especially for PCM_CLK 2 EG18 works as a master device pertaining to I2C interface 3 13 ADC Interfaces The module provides two Analog to Digital Converters ADC ...

Page 59: ... 3 14 Network Status Indication The network indication pins can be used to drive network status indication LEDs The following tables describe pin definition and logic level changes in different network status Table 21 Pin Definition of Network Status Activity Indicator Pin Name Pin No Description ADC0 173 General purpose analog to digital converter interface If unused keep it open ADC1 175 General...

Page 60: ...re 30 Reference Circuit of the Network Indicator NET_STATUS 170 DO Indicate the module s network activity status 1 8V power domain If unused keep it open Pin Name Status Description NET_MODE Always High Registered on network Always Low Others NET_STATUS Flicker slowly 200ms High 1800ms Low Network searching Flicker slowly 1800ms High 200ms Low Idle Flicker quickly 125ms High 125ms Low Data transfe...

Page 61: ... as below 4 7K 47K VBAT 2 2K Module STATUS Figure 31 Reference Circuits of STATUS 3 16 RI Behaviors AT QCFG risignaltype physical command can be executed to configure RI behaviors No matter on which port a URC is presented the URC will trigger the behavior of RI pin The URC can be output from UART port USB AT port and USB modem port by executing AT QURCCFG command The default port is USB AT port P...

Page 62: ...I Express Specification Revision 2 1 compliance Data rate at 5Gbps per lane Can be used to connect to an external Ethernet IC MAC and PHY or WLAN IC The following table shows the pin definition of PCIe interface Table 25 Pin Definition of the PCIe Interface State Response Idle RI keeps at high level URC RI outputs 120ms low pulse when a new URC returns Pin Name Pin No I O Description Comment PCIE_...

Page 63: ...LK_REQ_N 188 IO PCIe clock request In master mode it is an input signal In slave mode it is an output signal If unused keep it open PCIE_RST_N 189 IO PCIe reset In master mode it is an output signal In slave mode it is an input signal If unused keep it open PCIE_WAKE_N 190 IO PCIe wake In master mode it is an input signal In slave mode it is an output signal If unused keep it open NOTE ...

Page 64: ...ference circuit of PCIe RC mode GND PCIE_TX_M PCIE_TX_P GND PCIE_RX_M PCIE_RX_P PCIE_RX_M PCIE_RX_P PCIE_TX_M PCIE_TX_P C3 C4 C1 C2 100nF 100nF 100nF 100nF Module WLAN PCIE_REFCLK_P PCIE_REFCLK_M PCIE_REFCLK_P PCIE_REFCLK_M PCIE_RST_N PCIE_CLKREQ_N PCIE_WAKE_N PCIE_RST_N PCIE_CLKREQ_N PCIE_WAKE_N R2 100K R1 100K VDD_EXT NM R3 Wi Fi Antenna Figure 32 PCIe Interface Reference Circuit RC Mode ...

Page 65: ...REQ_N PCIE_WAKE_N PCIE_RST_N PCIE_CLKREQ_N PCIE_WAKE_N R6 100K R5 100K VDD_EXT R7 NM Figure 33 PCIe Interface Reference Circuit EP Mode In order to ensure the signal integrity of PCIe interface C1 and C2 have been placed inside the module C3 and C4 should be placed close to the host and R1 R2 R3 and R4 should be placed close to the module and also close to each other The extra stubs of trace must ...

Page 66: ...st be realized over USB 2 0 while GNSS NMEA output and software debugging can be realized over USB 2 0 3 0 USB 2 0 is recommended 3 18 SDIO Interface EG18 provides one SDIO interface which supports SD 3 0 protocol and eMMC The following table shows the pin definition Table 26 Pin Definition of SDIO Interface Pin Name Pin No I O Description Comment SD_VDD 46 PO SD card application SDIO pull up powe...

Page 67: ... among 10kΩ 100kΩ and the recommended value is 100kΩ In order to improve signal quality it is recommended to add 0Ω resistors R1 to R6 in series between the module and the SD card The bypass capacitors C1 to C6 are reserved and not mounted by default All resistors and bypass capacitors should be placed close to the module In order to offer good ESD protection it is recommended to add a TVS diode o...

Page 68: ...Module Tuner RFFE_CLK RFFE_DATA VDD_EXT VDD_RF 71 73 168 162 SCLK SDATA VIO VDD Figure 32 Sketch map of MIPI Tuner control Table 28 Pin Definition of GPIO Interface Used to Control Antenna Tuner Pin Name Pin No I O Description Comment RFFE_CLK 71 DO RFFE serial interface used for external tuner control If unused keep it open RFFE_DATA 73 IO If unused keep it open VDD_EXT 168 PO Provide 1 8V for ex...

Page 69: ... upgrade over USB interface Table 29 Pin Definition of USB_BOOT Interface The following figure shows a reference circuit of USB_BOOT interface Module USB_BOOT VDD_EXT 10K Test Point TVS Close to module Figure 35 Reference Circuit of USB_BOOT Interface GPIO_5 172 IO If unused keep it open VDD_RF 162 PO Provide 2 85V for external RF circuit If unused keep it open Pin Name Pin No I O Description Comm...

Page 70: ...ion to the three GPIOs dedicated for external tuner control the module provides 2 GPIOs for customers design Table 30 Pin Definition of GPIOs Pin Name Pin No I O Description Comment GPIO_1 138 IO General purpose input output port If unused keep it open GPIO_2 139 IO If unused keep it open ...

Page 71: ...interface by default By default EG18 GNSS engine is switched off It has to be switched on via AT command For more details about GNSS engine technology and configurations please refer to document 4 4 2 GNSS Performance The following table shows GNSS performance of EG18 Table 31 GNSS Performance Parameter Description Conditions Typ Unit Sensitivity GNSS Cold start Autonomous 147 dBm Reacquisition Au...

Page 72: ... such as U SIM card USB interface camera module display connector and SD card should be kept away from the antennas Use ground vias around the GNSS trace and sensitive analog signal traces to provide coplanar isolation and protection Keep the characteristic impedance for ANT_GNSS trace to 50Ω Please refer to Chapter 5 for GNSS reference design and antenna installation Hot start open sky Autonomous...

Page 73: ...MIMO antenna interfaces is shown as below Table 32 Pin Definition of the Main Rx diversity MIMO Antenna Interfaces 5 1 2 Operating Frequencies Table 33 EG18 EA Operating Frequencies Pin Name Pin No I O Description Comment ANT_MAIN 107 IO Main antenna interface 50Ω impedance ANT_DIV 127 AI Rx diversity antenna interface 50Ω impedance ANT_MIMO1 101 AI 4 4 MIMO antenna interface 50Ω impedance ANT_MIM...

Page 74: ... 802 9 MHz LTE B38 2570 2619 9 2570 2619 9 MHz LTE B40 2300 2399 9 2300 2399 9 MHz LTE B41 2496 2689 9 2496 2689 9 MHz 3GPP Band Transmit Receive Unit WCDMA B2 1850 1910 1930 1990 MHz WCDMA B4 1710 1755 2110 2155 MHz WCDMA B5 824 849 869 894 MHz LTE B2 1850 1910 1930 1990 MHz LTE B4 1710 1755 2110 2155 MHz LTE B5 824 849 869 894 MHz LTE B7 2500 2570 2620 2690 MHz LTE B12 699 716 729 746 MHz LTE B1...

Page 75: ...ounted according to the actual debugging C1 to C8 are not mounted and a 0Ω resistor is mounted on R1 to R4 respectively by default ANT_MAIN R1 0R C1 Module Main Antenna NM C2 NM R3 0R C5 MIMO Antenna NM C6 NM ANT_DIV R2 0R C3 NM C4 NM ANT_MIMO1 C7 NM C8 NM ANT_MIMO2 MIMO Antenna Diversity Antenna R4 0R Figure 36 Reference Circuit of RF Antenna Interfaces Please keep a proper distance between the m...

Page 76: ...ency specification of GNSS antenna interface Table 35 Pin Definition of GNSS Antenna Interface 5 2 2 GNSS Frequency Table 36 GNSS Frequency Pin Name Pin No I O Description Comment ANT_GNSS 119 AI GNSS antenna interface 50Ω impedance Type Frequency Unit GPS 1575 42 1 023 MHz GLONASS 1597 5 1605 8 MHz Galileo 1575 42 2 046 MHz BeiDou 1561 098 2 046 MHz QZSS 1575 42 MHz ...

Page 77: ... of GNSS antenna is shown as below GNSS Antenna VDD Module ANT_GNSS 47nH 10R 0 1μF 0R NM NM 100pF Figure 37 Reference Circuit of GNSS Antenna Interface 1 An external LDO can be selected to supply power according to the active antenna requirement 2 If the module is designed with a passive antenna then the VDD circuit is not needed NOTES ...

Page 78: ...constant height from the reference ground to the signal layer H and the spacing between RF traces and grounds S Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance The following are reference designs of microstrip or coplanar waveguide with different PCB structures Figure 38 Microstrip Design on a 2 layer PCB Figure 39 Coplanar Waveguide Design on a ...

Page 79: ...races should be changed to curved ones There should be clearance under the signal pin of the antenna connector or solder joint The reference ground of RF traces should be complete Meanwhile adding some ground vias around RF traces and the reference ground could help to improve RF performance The distance between the ground vias and RF traces should be no less than two times as wide as RF signal tr...

Page 80: ...RF connector is used for antenna connection it is recommended to use the U FL R SMT connector provided by Hirose Figure 42 Dimensions of the U FL R SMT Connector Unit mm Active antenna gain 0dBi Active antenna embedded LNA gain 17dB WCDMA LTE VSWR 2 Efficiency 30 Max Input Power 50W Input Impedance 50Ω Cable Insertion Loss 1dB WCDMA B5 B8 LTE B5 B8 B12 B13 B14 B20 B26 B28 B29 B71 Cable Insertion L...

Page 81: ...l connector listed in the following figure can be used to match the U FL R SMT Figure 43 Mechanicals of U FL LP Connectors The following figure describes the space factor of mating plugs Figure 44 Space Factor of Mating Plugs Unit mm For more details please visit http www hirose com ...

Page 82: ...m ratings for power supply and voltage on digital and analog pins of the module are listed in the following table Table 38 Absolute Maximum Ratings Parameter Min Max Unit VBAT_RF VBAT_BB 0 3 4 7 V USB_VBUS 0 3 5 5 V Peak Current of VBAT_BB 0 1 2 A Peak Current of VBAT_RF 0 1 5 A Voltage at Digital Pins 0 3 2 3 V Voltage at ADC0 0 1 875 V Voltage at ADC1 0 1 875 V ...

Page 83: ... make certain functions of the module such as voice SMS data transmission to be realized Only one or more parameters like Pout might reduce in their value and exceed the specified tolerances When the temperature returns to normal operating temperature levels the module will meet 3GPP specifications again Parameter Description Conditions Min Typ Max Unit VBAT VBAT_BB and VBAT_RF The actual input vo...

Page 84: ...nnected 1 49 mA LTE FDD PF 32 USB disconnected 4 32 mA LTE FDD PF 64 USB disconnected 2 74 mA LTE FDD PF 128 USB disconnected 2 11 mA LTE FDD PF 256 USB disconnected 1 72 mA LTE TDD PF 32 USB disconnected 4 39 mA LTE TDD PF 64 USB disconnected 2 87 mA LTE TDD PF 128 USB disconnected 2 21 mA LTE TDD PF 256 USB disconnected 1 78 mA WCDMA PF 64 USB Suspend 2 74 mA LTE FDD PF 64 USB Suspend 2 83 mA LT...

Page 85: ... HSUPA CH4407 23 3dBm 539 mA WCDMA B8 HSDPA CH3012 23 3dBm 569 mA WCDMA B8 HSUPA CH3012 23 4dBm 571 mA IVBAT LTE data transfer GNSS OFF LTE FDD B1 CH300 23 4dBm 550 mA LTE FDD B3 CH1575 23 3dBm 606 mA LTE FDD B5 CH2525 23 1dBm 515 mA LTE FDD B7 CH3100 23 1dBm 764 mA LTE FDD B8 CH3625 23 2dBm 571 mA LTE FDD B20 CH6300 23 1dBm 540 mA LTE FDD B28 CH9435 23 1dBm 533 mA LTE TDD B38 CH38000 23 3dBm 352 ...

Page 86: ... USB disconnected 4 55 mA LTE FDD PF 64 USB disconnected 3 11 mA LTE FDD PF 128 USB disconnected 2 45 mA LTE FDD PF 256 USB disconnected 2 07 mA LTE TDD PF 32 USB disconnected 4 49 mA LTE TDD PF 64 USB disconnected 3 11 mA LTE TDD PF 128 USB disconnected 2 44 mA LTE TDD PF 256 USB disconnected 2 1 mA WCDMA PF 64 USB Suspend 2 89 mA LTE FDD PF 64 USB Suspend 3 49 mA LTE TDD PF 64 USB Suspend 3 49 m...

Page 87: ...TE data transfer GNSS OFF LTE FDD B2 CH900 23 3dBm 748 15 mA LTE FDD B4 CH2175 23 4dBm 652 72 mA LTE FDD B5 CH2525 22 83dBm 523 46 mA LTE FDD B7 CH3100 22 85dBm 894 89 mA LTE FDD B12 CH5095 22 86dBm 517 59 mA LTE FDD B13 CH5230 23 1dBm 587 83 mA LTE FDD B14 CH5330 23 35dBm 530 37 mA LTE FDD B25 CH8365 23 34dBm 770 79 mA LTE FDD B26 CH8865 23 39dBm 586 49 mA LTE FDD B30 CH9820 23 35dBm 797 07 mA LT...

Page 88: ... Frequency Max Min WCDMA bands 24dBm 1 3dB 50dBm LTE FDD bands 23dBm 2dB 40dBm LTE TDD bands 23dBm 2dB 40dBm Frequency Primary Diversity SIMO 1 3GPP SIMO WCDMA B1 110 5dBm 111dBm 113 5dBm 106 7dBm WCDMA B3 110dBm 110 5dBm 113 5dBm 103 7dBm WCDMA B5 111dBm 112dBm 114 5dBm 104 7dBm WCDMA B8 110dBm 111 5dBm 114dBm 103 7dBm LTE FDD B1 10M 98 2dBm 98 7dBm 101 2dBm 96 3dBm LTE FDD B3 10M 98 9dBm 98 6dBm...

Page 89: ...Bm 109 5dBm 112 5dBm 106 7dBm WCDMA B5 110 5dBm 111dBm 113dBm 104 7dBm LTE FDD B2 10M 98 7dBm 97 3dBm 101 3dBm 94 3dBm LTE FDD B4 10M 98 6dBm 97 8dBm 101 2dBm 96 3dBm LTE FDD B5 10M 98 1dBm 100 2dBm 102 7dBm 94 3dBm LTE FDD B7 10M 97 5dBm 99dBm 99 7dBm 94 3dBm LTE FDD B12 10M 99 6dBm 101 2dBm 103 0dBm 93 3dBm LTE FDD B13 10M 99 2dBm 101dBm 102 6dBm 93 3dBm LTE FDD B14 10M 98 6dBm 101 2dBm 102 4dBm...

Page 90: ... to achieve better performance of the module it is recommended to comply with the following principles for thermal considerations For PCB design please keep placement of the module away from heat sources especially high power components such as ARM processor audio power amplifier power supply etc Do not place components on the opposite side of the PCB area where the module is mounted and do not fi...

Page 91: ... figures manifest two kinds of heatsink designs for reference Please choose one or both of them according to particular application structure Heatsink EG18 Module Application Board Application Board Heatsink Thermal Pad Shielding Cover Figure 45 Reference Design of Heatsink Heatsink at the Top of the Module Thermal Pad Heatsink Application Board Application Board Heatsink Thermal Pad EG18 Module S...

Page 92: ...ect the components from damage the thermal design should be optimized to guarantee that the module s internal temperature maintains below 105 C constantly AT QTEMP command can be used to obtain the module s internal temperature As shown in the figure below Figure 47 Response of AT QTEMP ...

Page 93: ...mperature sensors of the EG18 Figure 48 Temperature Sensor Distribution 1 Make sure that the PCB design provides sufficient cooling solutions for the module proper mounting heatsinks and active cooling may be required depending on the integrated application 2 For more detailed guidelines on thermal design please refer to document 8 NOTES ...

Page 94: ...chanical Dimensions This chapter describes the mechanical dimensions of the module All dimensions are measured in mm and dimensional tolerances are 0 05mm unless otherwise specified 7 1 Mechanical Dimensions of the Module Pin1 Figure 49 Module Top and Side Dimensions Unit mm ...

Page 95: ...LTE A Module Series EG18 Hardware Design EG18_Hardware_Design 94 104 Figure 50 Module Bottom Dimensions Top View Unit mm ...

Page 96: ...are Design EG18_Hardware_Design 95 104 7 2 Recommended Footprint Figure 51 Recommended Footprint Top View Unit mm For easy maintenance of the module please keep about 3mm between the module and other components in the host PCB NOTE ...

Page 97: ...8_Hardware_Design 96 104 7 3 Top and Bottom Views of the Module Figure 52 Top View of the Module Figure 53 Bottom View of the Module These are rendering images of EG18 For authentic appearance please refer to the module received from Quectel NOTE ...

Page 98: ...actory environment of 30º C 60 RH Stored at 10 RH 3 Devices require baking before mounting if any circumstance below occurs When the ambient temperature is 23º C 5º C and the humidity indicator card shows the humidity is 10 before opening the vacuum sealed bag Device mounting cannot be finished within 168 hours at factory conditions of 30º C 60 RH 4 If baking is required devices may be baked for 8...

Page 99: ... is suggested that the peak reflow temperature is 238º C 245º C for SnAg3 0Cu0 5 alloy The absolute max reflow temperature is 245º C To avoid damage to the module caused by repeated heating it is strongly recommended that the module should be mounted after reflow soldering for the other side of PCB has been completed Recommended reflow soldering thermal profile is shown below Temp C Reflow Zone So...

Page 100: ...arriers Each reel is 10 56m long and contains 200 modules The figures below show the packaging details measured in mm Figure 55 Tape Specifications Unit mm Reflow Zone Max slope 2 to 3 C sec Reflow time D over 220 C 40 to 60 sec Max temperature 238 C 245 C Cooling down slope 1 to 4 C sec Reflow Cycle Max reflow cycle 1 ...

Page 101: ...LTE A Module Series EG18 Hardware Design EG18_Hardware_Design 100 104 Figure 56 Reel Specifications Unit mm ...

Page 102: ..._Note GNSS application note for EM12 EG12 and EG18 modules 5 Quectel_Module_Secondary_SMT_User_Guide Module Secondary SMT User Guide 6 Quectel_EM12 EG12 EG18_Reference_Design Reference design for EM12 EG12 and EG18 modules 7 Quectel_RF_Layout_Application_Note RF layout application note 8 Quectel_LTE_Module_Thermal_Design_Guide Thermal design guide for LTE modules 9 Quectel_EG06 EG12 EG18_Differenc...

Page 103: ...ssion EFR Enhanced Full Rate ESD Electrostatic Discharge ESR Equivalent Series Resistance FR Full Rate GLONASS GLObalnaya NAvigatsionnaya Sputnikovaya Sistema the Russian Global Navigation Satellite System GMSK Gaussian Minimum Shift Keying GNSS Global Navigation Satellite System GPS Global Positioning System HO RXD Higher order Receiver Diversity HR Half Rate I O Input Output Inorm Normal Current...

Page 104: ...Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying RF Radio Frequency RHCP Right Hand Circularly Polarized Rx Receive SGMII Serial Gigabit Media Independent Interface SIMO Single Input Multiple Output SMS Short Message Service TDD Time Division Duplexing Tx Transmitting Direction UL Uplink UMTS Universal Mobile Telecommunications System URC Unsolicited Result Code U SIM Universal S...

Page 105: ...Input Low Level Voltage Value VILmin Minimum Input Low Level Voltage Value VImax Absolute Maximum Input Voltage Value VImin Absolute Minimum Input Voltage Value VOHmax Maximum Output High Level Voltage Value VOHmin Minimum Output High Level Voltage Value VOLmax Maximum Output Low Level Voltage Value VOLmin Minimum Output Low Level Voltage Value VSWR Voltage Standing Wave Ratio ...

Page 106: ...tant Note notice that any deviation s from the defined parameters of the antenna trace as described by the instructions require that the host product manufacturer must notify to Quectel that they wish to change the antenna trace design In this case a Class II permissive change application is required to be filed by the USI or the host manufacturer can take responsibility through the change in FCC ...

Page 107: ...lar installation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one of the following measures Reorient or relocate the receiving antenna Increase the separation between the equipment and receiver Connect the equipment into an outlet on a circu...

Page 108: ... with any other transmitter or antenna As long as 2 conditions above are met further transmitter test will not be required However the OEM integrator is still responsible for testing their end product for any additional compliance requirements required with this module installed Radiation Exposure Statement This equipment complies with FCC radiation exposure limits set forth for an uncontrolled en...

Page 109: ...ted with minimum distance 20 cm between the radiator your body Déclaration d exposition aux radiations Cet équipement est conforme aux limites d exposition aux rayonnements ISED établies pour un environnement non contrôlé Cet équipement doit être installé et utilisé avec un minimum de 20 cm de distance entre la source de rayonnement et votre corps This device is intended only for OEM integrators u...

Page 110: ...nada n est plus considérécomme valide et l ID IC ne peut pas être utilisésur le produit final Dans ces circonstances l intégrateur OEM sera chargéde réévaluer le produit final y compris l é metteur et l obtention d une autorisation distincte au Canada End Product Labeling This transmitter module is authorized only for use in device where the antenna may be installed such that 20 cm may be maintain...

Page 111: ...s fournir des informations àl utilisateur final quant à la faç on d installer ou de supprimer ce module RF dans le manuel de l utilisateur du produit final qui intègre ce module Le manuel de l utilisateur final doit inclure toutes les informations ré glementaires requises et avertissements comme indiquédans ce manuel ...

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