LTE-A Module Series
EG18 Hardware Design
EG18_Hardware_Design 54 / 104
The following figure shows the timing of SPI Interface.
SPI_CS_N
SPI_CLK
SPI_MOSI
MSB
1
2
SPI_MISO
3
T
t(mov)
4
t(mis)
t(mih)
t(ch) t(cl)
Figure 26: Timing of SPI Interface
The related parameters of SPI timing are listed in the following table.
Table 17: Parameters of SPI Interface Timing
“*” means under development.
BT_RXD
165
DI
Can be multiplexed into SPI_MISO.
BT_RTS
166
DI
Can be multiplexed into SPI_CS.
Parameter
Description
Min.
Typ.
Max.
Unit
T
SPI clock period
20.0
-
-
ns
t(ch)
SPI clock high level time
9.0
-
-
ns
t(cl)
SPI clock low level time
9.0
-
-
ns
t(mov)
SPI master data output valid time
-5.0
-
5.0
ns
t(mis)
SPI master data input setup time
5.0
-
-
ns
t(mih)
SPI master data input hold time
1.0
-
-
ns
NOTE
