LTE-A Module Series
EP06 Series Hardware Design
EP06_Series_Hardware_Design 25 / 56
Clock and mode can be configured by
AT+QDAI
command, and the default configuration is master mode
using short frame synchronization format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. In addition,
the module
’s firmware has integrated the configuration on some PCM codec’s application with I2C
interface. Refer to
document [2]
for details about the
AT+QDAI
command.
The following figure shows a reference design of PCM interface with an external codec IC.
PCM_DIN
PCM_DOUT
PCM_SYNC
PCM_CLK
I2C_SCL
I2C_SDA
Codec
Module
1.8V
2.
2K
2.
2K
BCLK
FS
DACIN
ADCOUT
SCLK
SDIN
B
IA
S
MIC_BIAS
MIC+
MIC-
SPKOUT-
Figure 8: Reference Circuit of PCM Application with Audio Codec
1. It is recommended to reserve an RC (R = 22
Ω, C = 22 pF) circuit on the PCM lines, especially for
PCM_CLK.
2. The module works as a master device pertaining to I2C interface.
3.7. Control and Indicator Signals
The following table shows the pin definition of control and indicator signals.
Table 9: Pin Definition of Control and Indicator Signals
Pin No. Pin Name
I/O
Power
Domain
Description
Comment
1
WAKE_N*
OD
Output signal to wake up the host.
20
W_DISABLE_N*
DI
1.8 V
Airplane mode control
Active low.
22
RESET_N
DI
1.8 V
System reset.
Active low.
NOTES
