LTE-A Module Series
EP06 Series Hardware Design
EP06_Series_Hardware_Design 22 / 56
GND
USB3.0_TX-
USB3.0_TX+
GND
USB3.0_RX-
USB3.0_RX+
USB3.0_RX-
USB3.0_RX+
USB3.0_TX-
USB3.0_TX+
C3
C4
USB_DP
USB_DM
R1
R2
0R
0R
USB_D-
USB_D+
C1
C2
ESD Array
100nF
100nF
100nF
100nF
Module
MCU
R3
R4
NM_0R
NM_0R
Test Points
Minimize these stubs
Figure 5: Reference Circuit of USB 2.0 & 3.0 Interfaces
In order to ensure the signal integrity of USB data lines, C1 and C2 have been placed inside the module,
C3 and C4 should be placed close to the MCU, and R1, R2, R3 and R4 should be placed close to the
module and also close to each other. The extra stubs of trace must be as short as possible.
The following principles of USB interface design should be complied with, so as to meet USB 2.0 & USB
3.0 specifications.
It is important to route the USB signal traces as differential pairs with ground surrounded. The
impedance of USB differential trace is 90
Ω.
For USB 2.0 signal traces, the trace length difference of the differential pair should be less than 2
mm.
For USB 3.0 signal traces, the trace length difference of each differential pair (TX/RX) should be less
than 0.7 mm.
Do not route signal traces under crystals, oscillators, magnetic devices or RF signal traces. It is
important to route the USB 2.0 and 3.0 differential traces in inner-layer of the PCB, and surround the
traces with ground on that layer and with ground planes above and below.
If a USB connector is used, please keep the ESD protection components as close to the USB
connector as possible. Junction capacitance of the ESD protection device might cause influences on
USB 2.0 and 3.0 data lines, so please pay attention to the selection of the device. Typically, the stray
capacitance should be less than 2.0 pF for USB 2.0, and less than 0.4 pF for USB 3.0.
If possible, reserve a 0
Ω resistor on USB_D+ and USB_D- lines, respectively.
