LTE-A Module Series
EM121R-GL Hardware Design
EM121R-GL Hardware Design 41 / 80
than 1.0 pF for USB 2.0, and less than 0.15 pF for USB 3.0.
⚫
Keep the ESD protection devices as close to the USB connector as possible.
⚫
If possible, reserve 0 Ω resistors on USB_DP and USB_DM lines respectively.
4.3. PCIe Interface
The module provides one integrated PCIe interface, featuring as follows:
⚫
PCI Express Base Specification Revision 2.0
compliant
⚫
Data rate up to 5 Gbps per lane
4.3.1. Pin definition of PCIe
Table 15: Pin Definition of PCIe Interface
Pin No
.
Pin Name
I/O
Description
Comment
55
PCIE_REFCLK_P
AIO
PCIe reference clock (+)
100 MHz clock
frequency.
Require differential
impedance of 95 Ω
53
PCIE_REFCLK_M
AIO
PCIe reference clock (-)
49
PCIE_RX_P
AI
PCIe receive (+)
Require differential
impedance of 95 Ω
47
PCIE_RX_M
AI
PCIe receive (-)
43
PCIE_TX_P
AO
PCIe transmit (+)
Require differential
impedance of 95 Ω
41
PCIE_TX_M
AO
PCIe transmit (-)
50
PCIE_RST_N
DI, OD
PCIe reset.
Active LOW.
52
PCIE_CLKREQ_N
DO, OD
PCIe clock request.
Active LOW.
54
PCIE_WAKE_N
DO, OD
PCIe wake up.
Active LOW.