5G Module Series
RM500Q-GL Hardware Design
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4.3.4. PCIe Timing
The following figure is PCIe power-up timing sequence for an adapter powered from system power rail in
PCI Express M.2 specification.
Figure 20: PCIe Power-on Timing Requirements of M.2 Specification
The following table is power-up timing variables in PCI Express M.2 specification.
Table 17: Power-up Timing of M.2 Specification
Symbol
Min.
Typ.
Max.
Comment
T
PVPGL
50 ms
-
-
Power valid to PERST# input inactive
T
PERST#-CLK
100
μs
-
-
REFCLK stable before PERST# inactive
