INTRODUCTION
LIST OF FIGURES
Figure 1. QS-200M/QS-300M board layout . . . . . 2
Figure 2. 16450/16550 internal registers . . . . 3
Figure 3. Interrupt enable register . . . . . . 4
Figure 4. Interrupt identification register . . 5
Figure 5. Interrupt source identification . . . 6
Figure 6. FIFO control register
* . . . . . . . . 7
Figure 7. FIFO receiver trigger levels
* . . . . . 7
Figure 8. Line control register . . . . . . . . 8
Figure 9. Parity options . . . . . . . . . . . . 9
Figure 10. Word length and stop bit options . . . 9
Figure 11. MODEM control register . . . . . . . . 10
Figure 12. Line status register . . . . . . . . . 11
Figure 13. MODEM status register . . . . . . . . 13
Figure 14. Clock options . . . . . . . . . . . . 15
Figure 15. Divisor latch options . . . . . . . . 15
Figure 16. Address selection switches . . . . . . 16
Figure 17. Address selection examples . . . . . . 17
Figure 18. Interrupt selection jumper . . . . . . 18
Figure 19. Interrupt status register selection . 19
Figure 20. Interrupt status register definition . 19
Figure 21. Half duplex configuration jumpers . . 20
Figure 22. Output connectors . . . . . . . . . . 21
* For optional 16550 only.
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