BAUD RATE SELECTION
J1 J1
+-----------+ +-----------+
4| _ _+ _ |6 4| _ _--_ |6
1| _ _+ _ |3 1| _--_ _ |3
+-----------+ +-----------+
(a) ÷1 input clock (b) ÷2 input clock
J1 J1
+-----------+ +-----------+
4| _--_ _ |6 4| _+ _--_ |6
1| _ _--_ |3 1| _+ _--_ |3
+-----------+ +-----------+
(c) ÷5 input clock (d) ÷10 input clock
F i g u r e 1 4 . I n p u t C l o c k F r e q u e n c y O p t i o n s . F o r
c o m p a t i b i l i t y , t h e j u m p e r s h o u l d b e s e t
at ÷10 ( 18.432 MHz ÷ 10 = 1.8432 MHz ).
+-----------+-------------+-----------------------+
| Desired | Divisor | Error Between Desired |
| Baud Rate | Latch Value | and Actual Value (%) |
+-----------+-------------+-----------------------+
| 50 | 2304 | - |
| 75 | 1536 | - |
| 110 | 1047 | 0.026 |
| 150 | 768 | - |
| 300 | 384 | - |
| 600 | 192 | - |
| 1200 | 96 | - |
| 1800 | 64 | - |
| 2000 | 58 | 0.69 |
| 2400 | 48 | - |
| 3600 | 32 | - |
| 4800 | 24 | - |
| 7200 | 16 | - |
| 9600 | 12 | - |
| 19200 | 6 | - |
| 38400 | 3 | - |
| 56000 | 2 | 2.86 |
+-----------+-------------+-----------------------+
F i g u r e 1 5 . D i v i s o r l a t c h s e t t i n g s f o r c o m m o n b a u d
r a t e s u s i n g a n 1 . 8 4 3 2 M H z i n p u t c l o c k .
F o r c o m p a t i b i l i t y , c o n n e c t j u m p e r i n t h e
divide by 10 configuration (figure 14(d)).
