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    INSTALLATION

      X .     I N S T A L L A T I O N

1.  Set base address switches and interrupt and

   output configuration jumpers on the card.

2.  Turn unit off.
3.  Remove system cover as instructed in the 

   computer reference guide.

4.  Insert card into a vacant slot following  

   the guidelines for installation.

5.  Replace system cover.

     X I .     S P E C I F I C A T I O N S

   Bus interface:      IBM 8-bit bus (PC/XT)
   Dimensions:         8.25" x 3.9"

   Controllers:        4 - 16450 Asynchronous
                           Communication Elements
   Transmit drivers:   MC3487 or compatible
   Receive buffers:    MC3486 or compatible
   RS-422 interface:   4 - RJ-11 shielded connectors
   I/O Address range:  0000-FFFFH (See section VI)
   Interrupt levels:   IRQ 2(9),3-7

   Power requirements:
           +--------+--------+-----------+
           |   I

T    |  I MS    |  Supply   |

           +--------+--------+-----------+
           |  501mA |  576mA |  +5 Volts |
           +--------+--------+-----------+
           |   --   |   --   | +12 Volts |
           +--------+--------+-----------+
           |   --   |   --   | -12 Volts |
           +--------+--------+-----------+
         I T  - Typical adapter current
         I MS  - Maximum statistical adapter current

Summary of Contents for QS-300M

Page 1: ...ough every attempt has been made to guarantee the accuracy of this manual Qua Tech Inc assumes no l i a b i l i t y f o r d a m a g e s r e s u l t i n g f r o m e r r o r s i n t h i s document Qua T...

Page 2: ...5 C FIFO CONTROL REGISTER 7 D LINE CONTROL REGISTER 8 E MODEM CONTROL REGISTER 10 F LINE STATUS REGISTER 11 G MODEM STATUS REGISTER 13 H SCRATCHPAD REGISTER 14 IV FIFO INTERRUPT MODE OPERATION 14 V B...

Page 3: ...arity options 9 Figure 10 Word length and stop bit options 9 Figure 11 MODEM control register 10 Figure 12 Line status register 11 Figure 13 MODEM status register 13 Figure 14 Clock options 15 Figure...

Page 4: ...range o f a d d r e s s c h o i c e s b e t w e e n 0 a n d F F F F h e x T h e Q S 2 0 0 M Q S 3 0 0 M h a s t h e o p t i o n o f s e l e c t i n g o n e o f s i x possible Interrupt Request lines I...

Page 5: ...BOARD DESCRIPTION Figure 1 QS 200M QS 300M board layout...

Page 6: ...bits Independent and prioritized transmit receive and status interrupts Transmitter clock output to drive receive logic External receiver clock input The following pages provide a brief summary of th...

Page 7: ...rrupt When set logic 1 enables interrupt on clear to send data set ready ring indicator and data carrier detect ELSI Receiver Line Status Interrupt When set logic 1 enables interrupt on overrun parity...

Page 8: ...e When logic 1 indicates FIFO mode enabled IIDx Interrupt Identification Indicates highest priority interrupt pending if a n y S e e I P a n d f i g u r e 5 N O T E I I D 2 i s always a logic 0 in cha...

Page 9: ...mode Indicates the receiver FIFO trigger level has been reached The interrupt is reset when the FIFO drops below the the trigger level Character Timeout FIFO mode only Indicates no characters have bee...

Page 10: ...igger level for the receiver FIFO interrupt as given in figure 7 below RCVR FIFO RXT1 RXT0 Trigger level bytes 0 0 1 0 1 4 1 0 8 1 1 14 Figure 7 FIFO Trigger Levels DMAM DMA Mode Select When set logic...

Page 11: ...r a r e w r i t t e n t o o r t h e b i t s w i l l b e ignored I I I D LINE CONTROL REGISTER D7 DLAB Divisor latch access bit D6 BKCN Break control D5 STKP Stick parity D4 EPS Even parity select D3...

Page 12: ...and figure 9 STKP EPS PEN Parity x x 0 None 0 0 1 Odd 0 1 1 Even 1 0 1 Logic 1 1 1 1 Logic 0 Figure 9 16450 Parity Selections STB Number of Stop Bits Sets the number of stop bits transmitted See WLSx...

Page 13: ...eceive data paths Transmitter and receiver i n t e r r u p t s s t i l l o p e r a t e n o r m a l l y M O D E M c o n t r o l i n t e r r u p t s a r e a v a i l a b l e b u t a r e n o w controlled...

Page 14: ...m i n g e r r o r s o r b r e a k i n d i c a t i o n s i n t h e r e c e i v e r FIFO FFRX is reset by reading the line status register TEMT Transmitter Empty Indicates the transmitter holding regis...

Page 15: ...s to the mark state logic 1 and a valid start bit is received FE Framing Error Indicates the received character had an invalid stop bit The stop bit following the last data or parity bit was a 0 bit s...

Page 16: ...nput DSR Data Set Ready Complement of the DSR input CTS Clear To Send Complement of the CTS input Bits DDCD TERI DDSR and DCTS are the sources of MODEM status interrupts These bits are reset when the...

Page 17: ...s cleared when the FIFO is empty V BAUD RATE SELECTION The 16450 ACE determines the baud rate of the serial o u t p u t a n d u s e s a c o m b i n a t i o n o f t h e c l o c k i n p u t frequency an...

Page 18: ...e set at 10 18 432 MHz 10 1 8432 MHz Desired Divisor Error Between Desired Baud Rate Latch Value and Actual Value 50 2304 75 1536 110 1047 0 026 150 768 300 384 600 192 1200 96 1800 64 2000 58 0 69 24...

Page 19: ...ing accessed A switch in the ON position indicates that the corresponding address bit be a logic 0 for selection A switch in the OFF position forces the corresponding address bit to be a logic 1 for s...

Page 20: ...0 0 0 2 1 0 0 0 0 3 0 0 0300H BASE ADDRESS 06A0H 1 2 3 4 5 6 1 2 3 4 5 6 On _ _ _ _ _ _ _ _ _ _ _ Off 0 0 0 0 0 4 2 0 8 0 2 0 6 A 0 06A0H BASE ADDRESS 5220H 1 2 3 4 5 6 1 2 3 4 5 6 On _ _ _ _ _ _ _ _...

Page 21: ...hanged through a hardware jumper J3 as shown below Source 1 7 _ _ IRQ 2 9 _ _ IRQ 3 _ _ IRQ 4 J3 _ _ IRQ 5 _ _ IRQ 6 _ _ IRQ 7 6 12 Figure 18 Interrupt level selection jumper T h e Q S 2 0 0 M Q S 3 0...

Page 22: ...gister a n d a l l o f t h e 1 6 4 5 0 1 6 5 5 0 s b e h a v e n o r m a l l y W h e n position 6 is in the ON position the Interrupt Status register overrides the ACEs internal Scratchpad register I...

Page 23: ...s set logic 1 the transmitter d r i v e r i s e n a b l e d f o r o u t p u t o n t h e c h a n n e l W h e n cleared logic 0 the transmitter output enters a high impedance state Full duplex operation...

Page 24: ...EXTERNAL CONNECTIONS IX EXTERNAL CONNECTIONS Figure 22 Output Connectors...

Page 25: ...ce system cover XI SPECIFICATIONS Bus interface IBM 8 bit bus PC XT Dimensions 8 25 x 3 9 Controllers 4 16450 Asynchronous Communication Elements Transmit drivers MC3487 or compatible Receive buffers...

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