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BAUD
RATE SELECTION

V . A D D R E S S I N G

          E a c h   c h a n n e l   o f   t h e   D S - 2 0 2   /   D S - 3 0 2   u s e s   e i g h t
c o n s e c u t i v e   I / O   a d d r e s s   l o c a t i o n s   i n   t h e   r a n g e   0   t o
0 7 F F   H e x .     T h e   b a s e   a d d r e s s   o f   c h a n n e l   1   i s   s e l e c t e d
u s i n g   d i p   s w i t c h   S W 1   w h i l e   t h e   b a s e   a d d r e s s   o f   c h a n n e l
2   i s   s e l e c t e d   u s i n g   S W 2 .     S w i t c h   p o s i t i o n s   1   -   8
c o n t r o l   t h e   s e l e c t i o n   o f   a d d r e s s   l i n e s   A 9   t h r o u g h   A 3
r e s p e c t i v e l y .     A   s w i t c h   s e t   t o   t h e   " O N "   p o s i t i o n
r e q u i r e s   t h e   c o r r e s p o n d i n g   a d d r e s s   b i t   t o   b e   " 0 "   f o r
c h a n n e l   s e l e c t i o n   w h i l e   a   s w i t c h   s e t   t o   t h e   " O F F "
p o s i t i o n   r e q u i r e s   t h e   a d d r e s s   b i t   t o   b e   " 1 " .     A d d r e s s
l i n e s   A 1 0   -   A 1 5   m u s t   b e   " 0 "   f o r   p o r t   s e l e c t i o n .     S o m e
address selection examples are given in figure 10.

          J u m p e r   J 4   i s   u s e d   t o   i n d e p e n d e n t l y   e n a b l e   o r
disable the communication channels. Connecting J4 pins
1   a n d   3   e n a b l e s   c h a n n e l   1   w h i l e   c o n n e c t i n g   J 4   p i n s   2
and 4 enables channel 2. A channel may be disabled by
r e m o v i n g   t h e   c o r r e s p o n d i n g   j u m p e r   f r o m   J 4 .     T h e   l a y o u t
of jumper J4 is shown in figure 11.

SW1
+----------------------------+
| 1 2 3 4 5 6 7 8 |
|ON +-++-++-++-++-++-++-++-+ |
| |_|| || || || || || || | |
| | ||_||_||_||_||_||_||_| |
| +-++-++-++-++-++-++-++-+ |
+----------------------------+

( a ) A d d r e s s s e l e c t i o n s w i t c h
f o r c h a n n e l 1 . S h o w n i s s e t t i n g
for base address 03F8H (COM1).

SW2
+----------------------------+
| 1 2 3 4 5 6 7 8 |
|ON +-++-++-++-++-++-++-++-+ |
| |_|| ||_|| || || || || | |
| | ||_|| ||_||_||_||_||_| |
| +-++-++-++-++-++-++-++-+ |
+----------------------------+

( b ) A d d r e s s s e l e c t i o n s w i t c h
f o r c h a n n e l 2 . S h o w n i s s e t t i n g
for base address 02F8H (COM2).

Figure 9. Address selection switches.

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Summary of Contents for DS-202

Page 1: ...anty rights Although every attempt has been made to guarantee the accuracy of this manual Quatech Inc assumes no liability for damages resulting from errors in this document Quatech Inc reserves the right to edit or append to this document at any time without notice Please complete the following information and r e t a i n f o r y o u r r e c o r d s H a v e t h i s i n f o r m a t i o n available...

Page 2: ...IDENTIFICATION REGISTER 5 FIFO CONTROL REGISTER 7 LINE CONTROL REGISTER 8 MODEM CONTROL REGISTER 10 LINE STATUS REGISTER 11 MODEM STATUS REGISTER 13 SCRATCHPAD REGISTER 14 FIFO INTERRUPT MODE OPERATION 14 IV BAUD RATE SELECTION 14 V ADDRESSING 16 VI INTERRUPTS 18 VII OUTPUT CONFIGURATIONS 19 VIII EXTERNAL CONNECTIONS 23 IX INSTALLATION 24 X SPECIFICATIONS 24 with optional 16550 i ...

Page 3: ...selections 15 Figure 8 Divisor latch options 15 Figure 9 Address selection switches 16 Figure 10 Address selection examples 17 Figure 11 Channel enable disable selection 17 Figure 12 System interrupt connection 18 Figure 13 Interrupt mode selection 18 Figure 14 Output control block diagram 19 Figure 15 Auxiliary channel jumper definition 20 Figure 16 Auxiliary channel signal selection 21 Figure 17...

Page 4: ... t i n g a n d o r s h a r i n g o n e o f s i x p o s s i b l e interrupt request lines IRQ 2 3 4 5 6 7 II BOARD DESCRIPTION A component diagram of the DS 202 DS 302 showing the locations of the 16450 ACEs configuration jumpers address selection switches and output connectors is shown in figure 1 The first communication channel is c o n t r o l l e d b y t h e A C E l a b e l e d U 7 s w i t c h ...

Page 5: ...Figure 1 DS 202 DS 302 component layout ...

Page 6: ...rioritized transmit receive and status interrupts The following pages provide a brief summary of the internal registers available within the 16450 and 16550 ACEs The registers are addressed as shown in figure 2 b e l o w R e g i s t e r s a n d f u n c t i o n s s p e c i f i c t o t h e optional 16550 are indicated with an asterisk DLAB A2 A1 A0 REGISTER DESCRIPTION 0 0 0 0 Receive buffer read on...

Page 7: ...tor and data carrier detect ELSI Receiver Line Status Interrupt When set logic 1 enables interrupts on o v e r r u n p a r i t y f r a m i n g e r r o r s a n d b r e a k indication ETBEI Transmitter Holding Register Empty Interrupt W h e n s e t l o g i c 1 e n a b l e s i n t e r r u p t s o n transmitter register empty ERBFI Received Data Available Interrupt W h e n s e t l o g i c 1 e n a b l ...

Page 8: ...ication Indicates highest priority interrupt pending if a n y S e e I P a n d f i g u r e 3 N O T E I I D 2 i s always a logic 0 in the 16450 and in the 16550 character mode IP Interrupt Pending W h e n l o g i c 0 i n d i c a t e s t h a t a n i n t e r r u p t i s p e n d i n g a n d t h e c o n t e n t s o f t h e i n t e r r u p t identification register may be used to determine the interrupt ...

Page 9: ... mode Indicates the receiver FIFO trigger level has been reached The interrupt is reset when the FIFO drops below the the trigger level Character Timeout FIFO mode only Indicates no characters have been removed from or input to the receiver FIFO for the last four c h a r a c t e r t i m e s a n d t h e r e i s a t l e a s t o n e character in the receiver FIFO The interrupt is cleared by reading t...

Page 10: ... e l f o r t h e F I F O interrupt as given in figure 4 below RCVR FIFO RXT1 RXT0 Trigger level bytes 0 0 1 0 1 4 1 0 8 1 1 14 Figure 4 FIFO trigger levels DMAM DMA Mode Select When set logic 1 RxRDY and TxRDY change from mode 0 to mode 1 DMA mode is not supported by the DS 202 DS 302 XRST Transmit FIFO Reset When set logic 1 all bytes in the transmitter FIFO are cleared and the counter is reset T...

Page 11: ... O c o n t r o l r e g i s t e r a r e w r i t t e n t o o r t h e b i t s w i l l b e ignored LINE CONTROL REGISTER D7 DLAB Divisor latch access bit D6 BKCN Break control D5 STKP Stick parity D4 EPS Even parity select D3 PEN Parity enable D2 STB Number of stop bits D1 WLS1 Word length select D0 WLS0 DLAB Divisor Latch Access Bit DLAB must be set to logic 1 to access the baud rate divisor latches ...

Page 12: ...STKP and figure 5 STKP EPS PEN Parity x x 0 None 0 0 1 Odd 0 1 1 Even 1 0 1 Logic 1 1 1 1 Logic 0 Figure 5 16450 16550 parity selections STB Number of Stop Bits Defines the number of stop bits per character See WLSx and figure 6 WLSx Word Length Select Defines the number of data bits per character See STB and figure 6 STB WLS1 WLS0 Word length Stop bits 0 0 0 5 bits 1 0 0 1 6 bits 1 0 1 0 7 bits 1...

Page 13: ...e d t h r o u g h t h e M O D E M c o n t r o l register B i t s O U T 2 O U T 1 R T S a n d D T R p e r f o r m i d e n t i c a l functions on their respective outputs When these b i t s a r e s e t l o g i c 1 i n t h e r e g i s t e r t h e a s s o c i a t e d o u t p u t i s f o r c e d t o a l o g i c 0 W h e n cleared logic 0 the output is forced to a logic1 OUT2 Output 2 C o n t r o l s t h...

Page 14: ... a k i n d i c a t i o n s i n t h e r e c e i v e r FIFO FFRX is reset by reading the line status register TEMT Transmitter Empty Indicates the transmitter holding register or F I F O a n d t h e t r a n s m i t t e r s h i f t r e g i s t e r a r e empty and are ready to receive new data TEMT i s r e s e t b y w r i t i n g a c h a r a c t e r t o t h e transmitter holding register THRE Transmit...

Page 15: ...ntil SIN goes to the mark state logic 1 and a valid start bit is received FE Framing Error Indicates the received character had an invalid stop bit The stop bit following the last data or parity bit was a 0 bit spacing level PE Parity Error Indicates that the received data does not have the correct parity OE Overrun Error Indicates the receive buffer was not read before t h e n e x t c h a r a c t...

Page 16: ...r To Send Complement of the CTS input Bits DDCD TERI DDSR and DCTS are the sources of MODEM status interrupts These bits are reset when the MODEM status register is read DDCD Delta Data Carrier Detect Indicates the Data Carrier Detect DCD input has changed state TERI Trailing Edge Ring Indicator I n d i c a t e s t h e R i n g I n d i c a t o r R I i n p u t h a s changed from a low to a high stat...

Page 17: ...pty IV BAUD RATE SELECTION The 16450 16550 ACE determines the baud rate of t h e s e r i a l o u t p u t u s i n g a c o m b i n a t i o n o f t h e i n p u t clock frequency and the value written to the baud rate divisor latches Standard PC PC XT PC AT and PS 2 serial interfaces use an input clock of 1 8432 MHz To i n c r e a s e v e r s a t i l i t y t h e D S 2 0 2 D S 3 0 2 u s e s a n 18 432 ...

Page 18: ... 432 MHz 10 1 8432 MHz Desired Divisor Error Between Desired Baud Rate Latch Value and Actual Value 50 2304 75 1536 110 1047 0 026 150 768 300 384 600 192 1200 96 1800 64 2000 58 0 69 2400 48 3600 32 4800 24 7200 16 9600 12 19200 6 38400 3 56000 2 2 86 Figure 8 Divisor latch s e t t i n g s f o r c o m m o n b a u d r a t e s u s i n g a 1 8 4 3 2 M H z i n p u t c l o c k T h e j u m p e r must b...

Page 19: ... F F position requires the address bit to be 1 Address lines A10 A15 must be 0 for port selection Some address selection examples are given in figure 10 J u m p e r J 4 i s u s e d t o i n d e p e n d e n t l y e n a b l e o r disable the communication channels Connecting J4 pins 1 and 3 enables channel 1 while connecting J4 pins 2 and 4 enables channel 2 A channel may be disabled by removing the ...

Page 20: ...F8H 1 2 3 4 5 6 7 8 ON _ _ _ _ _ _ _ _ 0 2 1 8 4 2 0 8 BASE ADDRESS 3 E 8 03E8H 1 2 3 4 5 6 7 8 ON _ _ _ _ _ _ _ _ 0 2 0 8 4 2 0 0 BASE ADDRESS 2 E 0 02E0H Figure 10 Address selection examples J4 3 _ _ 4 1 _ _ 2 enable channel 1 enable channel 2 Figure 11 Channel enable disable jumper Connecting pins 1 3 enables channel 1 Connecting pins 2 4 enables channel 2 ...

Page 21: ...a n n e l 1 J 6 f o r channel 2 An additional feature of the DS 202 DS 302 is the ability to share one interrupt level between both communication channels or to share an interrupt level with another Quatech adapter supporting this interrupt sharing capability Jumper J2 controls the interrupt sharing feature for channel 1 jumper J3 for channel 2 J2 J3 J2 J3 4 _ _ _ 6 4 _ _ _ 6 1 _ _ _ 3 1 _ _ _ 3 a...

Page 22: ...eceiver RCLK ___ DTR RxD ___ RS 422 485 DSR Receiver ___ DCD __ RI 16450 Figure 14 Output control block diagram Auxiliary Channel Configuration The function of jumpers J8 and J10 is to control t h e s o u r c e o f t h e i n f o r m a t i o n e x c h a n g e d o n t h e auxiliary communication lines The output sources are request to send RTS transmit clock XCLK and the auxiliary input AUXIN The in...

Page 23: ... 16b Transmission of XCLK can be used to synchronize communications with a peripheral or to provide a shift clock to a receiver XCLK is transmitted by connecting pins 5 and 6 of the jumper block figure 16b AUXIN is the auxiliary input from a peripheral device Connecting AUXIN to AUXOUT provides a loopback mode of operation That is whatever is transmitted by t h e p e r i p h e r a l w i l l b e f ...

Page 24: ...n XCLK transmission XCLK RCLK loopback RCLK reception AUXOUT RTS XCLK 4 _ _ _ 6 1 _ _ _ 3 CTS RCLK AUXIN c RTS CTS loopback XCLK RCLK loopback AUXOUT AUXIN loopback Figure 16 Auxiliary channel configuration Use J8 for channel 1 J10 for channel 2 driver enable 5 _ _ _ _ 8 1 _ _ _ _ 4 DTR DTR RTS RTS Figure 17 Half duplex control jumper Use J7 for channel 1 J9 for channel 2 ...

Page 25: ... h i m p e d a n c e state If the jumper is installed between pins 2 and 6 t h e l o g i c a l s e n s e o f D T R i s i n v e r t e d T h a t i s clearing DTR logic 0 enables the transmitter drivers while setting DTR logic 1 forces the outputs to a high impedance state If a jumper is installed between pins 3 and 7 the output drivers are controlled by the ACE s RTS signal Setting RTS logic 1 enabl...

Page 26: ...CRIPTION 1 AUXOUT When combine with AUXOUT provides the auxiliary channel output defined by jumper J8 J10 2 TxD When combined with TxD provides the serial data output 3 GND Chassis ground 4 RxD When combined with RxD provides the serial data input 5 AUXIN When combined with AUXIN provides the auxiliary channel input defined by jumper J8 J10 6 AUXOUT See AUXOUT 7 TxD See TxD 8 RxD See RxD 9 AUXIN S...

Page 27: ... 5 Replace system cover X SPECIFICATIONS Bus interface ISA 8 bit bus Controllers 2 16450 Asynchronous Communication Elements 16550 optional Interface 2 D 9 female connectors Transmit drivers MC3487 or compatible RS 422 TI75174 or compatible RS 485 Receive buffers MC3486 or compatible RS 422 TI75175 or compatible RS 485 I O Address range 0000H 07FFH Interrupt levels IRQ 2 3 4 5 6 7 Power requiremen...

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